learn the combinational and sequential logic circuit.
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May 11, 2025 - SystemVerilog
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fpga-programming
Here are 13 public repositories matching this topic...
An FPGA implementation of Cummings' Asynchronous FIFO
fpga rtl verilog xilinx synthesis systemverilog fifo uvm xilinx-fpga xilinx-vivado digilent hardware-description-language nexys4ddr universal-verification-methodology fpga-programming digilent-nexys-4-board synthesizable asynchronous-fifo uvm-verification register-transistor-level
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Apr 14, 2022 - SystemVerilog
ARM single cycle processor on nandland.com go-board
arm embedded fpga assembly assembler systemverilog hdl fpga-soc system-architecture ice40 system-design fpga-programming
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Oct 23, 2023 - SystemVerilog
Implementation of a generalized Parallel Multiplier using Carry Save Adder in SystemVerilog and Xilinx Vivado.
asic fpga rtl systemverilog verilog-hdl xilinx-vivado multiplier fpga-programming vlsi-design asic-design rtl-design parallel-multiplication systemverilog-test-bench register-transfer-level
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Dec 13, 2024 - SystemVerilog
SystemVerilog Solutions to exercise from HDLBits
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May 27, 2023 - SystemVerilog
learning about FPGA
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May 20, 2024 - SystemVerilog
This repository contains a SystemVerilog implementation of a basic 5-stage pipeline RISC-V processor. The processor includes a register file, ALU, control unit, instruction memory, and data memory. It is designed to run simple assembly programs and includes optimizations for performance such as hazard detection, forwarding, and branch prediction.
cpu fpga simulation processor riscv verilog assembly-language vivado systemverilog alu risc-v registers fpga-programming riscvprocessor
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Mar 2, 2025 - SystemVerilog
Implementation of a FIR-filter on a FPGA and its employment in an audio system obtained using a PMOD I2S2.
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Apr 22, 2025 - SystemVerilog
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.
simulation rtl verilog vivado uart systemverilog uart-verilog fpga-soc testbench verilog-hdl fpga-board vivado-hls nexys4ddr verilog-project uart-transmitter uart-receiver fpga-programming vivado-simulator
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Feb 28, 2025 - SystemVerilog
Here you'll find the game "Donkey Kong" written 100% in SysVerilog. You'll need an FPGA card, a screen, a keyboard, and audio devices for the full functionality.
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Oct 21, 2024 - SystemVerilog
A simple processor with a grid of cores that can only interact with their immediate neighbors
game-of-life linear-algebra cellular-automata gpu-acceleration partial-differential-equations heat-equation wave-equation cellular-automaton fpga-programming
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Feb 9, 2024 - SystemVerilog
🔋 SystemVerilog study repository
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Feb 15, 2023 - SystemVerilog
A slot machine created in System Verilog. It was built, simulated, synthesized, and implemented in Vivado, for use on the Xilinx Basys 3 board.
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Aug 24, 2023 - SystemVerilog
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