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[MSP430] Generate EABI-compliant libcalls #78

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May 13, 2017
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4 changes: 4 additions & 0 deletions include/llvm/IR/CallingConv.h
Original file line number Diff line number Diff line change
Expand Up @@ -196,6 +196,10 @@ namespace CallingConv {
/// Register calling convention used for parameters transfer optimization
X86_RegCall = 92,

/// Calling convention used for special MSP430 rtlib functions
/// which have an "optimized" convention using additional registers.
MSP430_BUILTIN = 94,

/// The highest possible calling convention ID. Must be some 2^k - 1.
MaxID = 1023
};
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1 change: 1 addition & 0 deletions lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4170,6 +4170,7 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) {
ReplacedNode(Node);
break;
}
case ISD::MUL:
case ISD::SDIV:
case ISD::SREM:
case ISD::UDIV:
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268 changes: 233 additions & 35 deletions lib/Target/MSP430/MSP430ISelLowering.cpp

Large diffs are not rendered by default.

2 changes: 1 addition & 1 deletion lib/Target/MSP430/MSP430InstrInfo.td
Original file line number Diff line number Diff line change
Expand Up @@ -209,7 +209,7 @@ let isCall = 1 in
// a use to prevent stack-pointer assignments that appear immediately
// before calls from potentially appearing dead. Uses for argument
// registers are added manually.
let Defs = [R12, R13, R14, R15, SR],
let Defs = [R11, R12, R13, R14, R15, SR],
Uses = [SP] in {
def CALLi : II16i<0x0,
(outs), (ins i16imm:$dst),
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4 changes: 2 additions & 2 deletions lib/Target/MSP430/MSP430RegisterInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -41,12 +41,12 @@ MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
const Function* F = MF->getFunction();
static const MCPhysReg CalleeSavedRegs[] = {
MSP430::FP, MSP430::R5, MSP430::R6, MSP430::R7,
MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
MSP430::R8, MSP430::R9, MSP430::R10,
0
};
static const MCPhysReg CalleeSavedRegsFP[] = {
MSP430::R5, MSP430::R6, MSP430::R7,
MSP430::R8, MSP430::R9, MSP430::R10, MSP430::R11,
MSP430::R8, MSP430::R9, MSP430::R10,
0
};
static const MCPhysReg CalleeSavedRegsIntr[] = {
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43 changes: 43 additions & 0 deletions test/CodeGen/MSP430/hwmult16.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
; RUN: llc -O0 -mhwmult=16bit < %s | FileCheck %s

target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
target triple = "msp430---elf"

@g_i32 = global i32 123, align 8
@g_i64 = global i64 456, align 8
@g_i16 = global i16 789, align 8

define i16 @mpyi() #0 {
entry:
; CHECK: mpyi:

; CHECK: call #__mspabi_mpyi_hw
%0 = load volatile i16, i16* @g_i16, align 8
%1 = mul i16 %0, %0

ret i16 %1
}

define i32 @mpyli() #0 {
entry:
; CHECK: mpyli:

; CHECK: call #__mspabi_mpyl_hw
%0 = load volatile i32, i32* @g_i32, align 8
%1 = mul i32 %0, %0

ret i32 %1
}

define i64 @mpylli() #0 {
entry:
; CHECK: mpylli:

; CHECK: call #__mspabi_mpyll_hw
%0 = load volatile i64, i64* @g_i64, align 8
%1 = mul i64 %0, %0

ret i64 %1
}

attributes #0 = { nounwind }
43 changes: 43 additions & 0 deletions test/CodeGen/MSP430/hwmult32.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
; RUN: llc -O0 -mhwmult=32bit < %s | FileCheck %s

target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
target triple = "msp430---elf"

@g_i32 = global i32 123, align 8
@g_i64 = global i64 456, align 8
@g_i16 = global i16 789, align 8

define i16 @mpyi() #0 {
entry:
; CHECK: mpyi:

; CHECK: call #__mspabi_mpyi_hw
%0 = load volatile i16, i16* @g_i16, align 8
%1 = mul i16 %0, %0

ret i16 %1
}

define i32 @mpyli() #0 {
entry:
; CHECK: mpyli:

; CHECK: call #__mspabi_mpyl_hw32
%0 = load volatile i32, i32* @g_i32, align 8
%1 = mul i32 %0, %0

ret i32 %1
}

define i64 @mpylli() #0 {
entry:
; CHECK: mpylli:

; CHECK: call #__mspabi_mpyll_hw32
%0 = load volatile i64, i64* @g_i64, align 8
%1 = mul i64 %0, %0

ret i64 %1
}

attributes #0 = { nounwind }
43 changes: 43 additions & 0 deletions test/CodeGen/MSP430/hwmultf5.ll
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
; RUN: llc -O0 -mhwmult=f5series < %s | FileCheck %s

target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16-a0:16:16"
target triple = "msp430---elf"

@g_i32 = global i32 123, align 8
@g_i64 = global i64 456, align 8
@g_i16 = global i16 789, align 8

define i16 @mpyi() #0 {
entry:
; CHECK: mpyi:

; CHECK: call #__mspabi_mpyi_f5hw
%0 = load volatile i16, i16* @g_i16, align 8
%1 = mul i16 %0, %0

ret i16 %1
}

define i32 @mpyli() #0 {
entry:
; CHECK: mpyli:

; CHECK: call #__mspabi_mpyl_f5hw
%0 = load volatile i32, i32* @g_i32, align 8
%1 = mul i32 %0, %0

ret i32 %1
}

define i64 @mpylli() #0 {
entry:
; CHECK: mpylli:

; CHECK: call #__mspabi_mpyll_f5hw
%0 = load volatile i64, i64* @g_i64, align 8
%1 = mul i64 %0, %0

ret i64 %1
}

attributes #0 = { nounwind }
2 changes: 1 addition & 1 deletion test/CodeGen/MSP430/jumptable.ll
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ entry:
store i16 %i, i16* %i.addr, align 2
%0 = load i16, i16* %i.addr, align 2
; CHECK: mov.w #2, r13
; CHECK: call #__mulhi3hw_noint
; CHECK: call #__mspabi_mpyi
; CHECK: br .LJTI0_0(r12)
switch i16 %0, label %sw.default [
i16 0, label %sw.bb
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