Misc doc fixes.

embedded-hal-async/README.md

@@ -7,16 +7,9 @@
 An asynchronous Hardware Abstraction Layer (HAL) for embedded systems.
 
 This crate contains asynchronous versions of the [`embedded-hal`](https://crates.io/crates/embedded-hal) traits and shares its scope and [design goals](https://docs.rs/embedded-hal/latest/embedded_hal/#design-goals).
-The purpose of this crate is to iterate over these trait versions before integrating them into [`embedded-hal`](https://crates.io/crates/embedded-hal).
-
-**NOTE** These traits are still experimental. At least one breaking change to this crate is expected in the future (changing from GATs to `async fn`), but there might be more.
 
 This project is developed and maintained by the [HAL team](https://github.com/rust-embedded/wg#the-hal-team).
 
-## [API reference]
-
-[API reference]: https://docs.rs/embedded-hal-async
-
 ## Minimum Supported Rust Version (MSRV)
 
 This crate requires Rust nightly newer than `nightly-2022-11-22`, due to requiring support for
@@ -30,8 +23,8 @@ at any time.
 Licensed under either of
 
 - Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or
-  http://www.apache.org/licenses/LICENSE-2.0)
-- MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT)
+  <http://www.apache.org/licenses/LICENSE-2.0>)
+- MIT license ([LICENSE-MIT](LICENSE-MIT) or <http://opensource.org/licenses/MIT>)
 
 at your option.
 

embedded-hal-async/src/lib.rs

@@ -1,12 +1,4 @@
-//! An asynchronous Hardware Abstraction Layer (HAL) for embedded systems
-//!
-//! **NOTE** These traits are still experimental. At least one breaking
-//! change to this crate is expected in the future (changing from GATs to
-//! `async fn`), but there might be more.
-//!
-//! **NOTE** The traits and modules in this crate should follow the same structure as in
-//! `embedded-hal` to ease merging and migration.
-
+#![doc = include_str!("../README.md")]
 #![warn(missing_docs)]
 #![no_std]
 #![allow(incomplete_features)]

embedded-hal-async/src/spi.rs

@@ -114,7 +114,7 @@ pub use spi_transaction as transaction;
 /// `SpiDevice` represents ownership over a single SPI device on a (possibly shared) bus, selected
 /// with a CS (Chip Select) pin.
 ///
-/// See (the docs on embedded-hal)[embedded_hal::spi::blocking] for important information on SPI Bus vs Device traits.
+/// See (the docs on embedded-hal)[embedded_hal::spi] for important information on SPI Bus vs Device traits.
 ///
 /// # Safety
 ///
@@ -239,7 +239,7 @@ unsafe impl<T: SpiDevice> SpiDevice for &mut T {
 pub trait SpiBusFlush: ErrorType {
     /// Wait until all operations have completed and the bus is idle.
     ///
-    /// See (the docs on embedded-hal)[embedded_hal::spi::blocking] for information on flushing.
+    /// See (the docs on embedded-hal)[embedded_hal::spi] for information on flushing.
     async fn flush(&mut self) -> Result<(), Self::Error>;
 }
 
@@ -257,7 +257,7 @@ pub trait SpiBusRead<Word: 'static + Copy = u8>: SpiBusFlush {
     /// typically `0x00`, `0xFF`, or configurable.
     ///
     /// Implementations are allowed to return before the operation is
-    /// complete. See (the docs on embedded-hal)[embedded_hal::spi::blocking] for details on flushing.
+    /// complete. See (the docs on embedded-hal)[embedded_hal::spi] for details on flushing.
     async fn read(&mut self, words: &mut [Word]) -> Result<(), Self::Error>;
 }
 
@@ -272,7 +272,7 @@ pub trait SpiBusWrite<Word: 'static + Copy = u8>: SpiBusFlush {
     /// Write `words` to the slave, ignoring all the incoming words
     ///
     /// Implementations are allowed to return before the operation is
-    /// complete. See (the docs on embedded-hal)[embedded_hal::spi::blocking] for details on flushing.
+    /// complete. See (the docs on embedded-hal)[embedded_hal::spi] for details on flushing.
     async fn write(&mut self, words: &[Word]) -> Result<(), Self::Error>;
 }
 
@@ -286,7 +286,7 @@ impl<T: SpiBusWrite<Word>, Word: 'static + Copy> SpiBusWrite<Word> for &mut T {
 ///
 /// `SpiBus` represents **exclusive ownership** over the whole SPI bus, with SCK, MOSI and MISO pins.
 ///
-/// See (the docs on embedded-hal)[embedded_hal::spi::blocking] for important information on SPI Bus vs Device traits.
+/// See (the docs on embedded-hal)[embedded_hal::spi] for important information on SPI Bus vs Device traits.
 pub trait SpiBus<Word: 'static + Copy = u8>: SpiBusRead<Word> + SpiBusWrite<Word> {
     /// Write and read simultaneously. `write` is written to the slave on MOSI and
     /// words received on MISO are stored in `read`.
@@ -298,7 +298,7 @@ pub trait SpiBus<Word: 'static + Copy = u8>: SpiBusRead<Word> + SpiBusWrite<Word
     /// typically `0x00`, `0xFF`, or configurable.
     ///
     /// Implementations are allowed to return before the operation is
-    /// complete. See (the docs on embedded-hal)[embedded_hal::spi::blocking] for details on flushing.
+    /// complete. See (the docs on embedded-hal)[embedded_hal::spi] for details on flushing.
     async fn transfer<'a>(
         &'a mut self,
         read: &'a mut [Word],
@@ -310,7 +310,7 @@ pub trait SpiBus<Word: 'static + Copy = u8>: SpiBusRead<Word> + SpiBusWrite<Word
     /// `words` buffer, overwriting it.
     ///
     /// Implementations are allowed to return before the operation is
-    /// complete. See (the docs on embedded-hal)[embedded_hal::spi::blocking] for details on flushing.
+    /// complete. See (the docs on embedded-hal)[embedded_hal::spi] for details on flushing.
     async fn transfer_in_place<'a>(&'a mut self, words: &'a mut [Word]) -> Result<(), Self::Error>;
 }
 

embedded-hal-bus/src/spi.rs

@@ -28,7 +28,7 @@ where
 
 /// [`SpiDevice`] implementation with exclusive access to the bus (not shared).
 ///
-/// This is the most straightforward way of obtaining an [`SpiDevice`] from an [`SpiBus`](embedded_hal::spi::blocking::SpiBus),
+/// This is the most straightforward way of obtaining an [`SpiDevice`] from an [`SpiBus`](embedded_hal::spi::SpiBus),
 /// ideal for when no sharing is required (only one SPI device is present on the bus).
 pub struct ExclusiveDevice<BUS, CS> {
     bus: BUS,

embedded-hal/src/lib.rs

@@ -35,7 +35,7 @@
 //!
 //! - Where possible must *not* be tied to a specific asynchronous model. The API should be usable
 //! in blocking mode, with the `futures` model, with an async/await model or with a callback model.
-//! (cf. the [`nb`] crate)
+//! (cf. the [`nb`](https://docs.rs/nb) crate)
 //!
 //! - Must be minimal, and thus easy to implement and zero cost, yet highly composable. People that
 //! want higher level abstraction should *prefer to use this HAL* rather than *re-implement*

embedded-hal/src/spi.rs

@@ -132,7 +132,7 @@
 //! # For HAL authors
 //!
 //! HALs **must** implement [`SpiBus`], [`SpiBusRead`] and [`SpiBusWrite`]. Users can combine the bus together with the CS pin (which should
-//! implement [`OutputPin`](crate::digital::blocking::OutputPin)) using HAL-independent [`SpiDevice`] implementations such as the ones in [`embedded-hal-bus`](https://crates.io/crates/embedded-hal-bus).
+//! implement [`OutputPin`](crate::digital::OutputPin)) using HAL-independent [`SpiDevice`] implementations such as the ones in [`embedded-hal-bus`](https://crates.io/crates/embedded-hal-bus).
 //!
 //! HALs may additionally implement [`SpiDevice`] to **take advantage of hardware CS management**, which may provide some performance
 //! benefits. (There's no point in a HAL implementing [`SpiDevice`] if the CS management is software-only, this task is better left to