Skip to content

BCM2711 KMS YUV Support #4754

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 14 commits into from
Dec 17, 2021
Merged

Conversation

mripard
Copy link
Contributor

@mripard mripard commented Dec 3, 2021

Hi,

This is another attempt of supporting YUV output in the HDMI driver following the discussions made on slack recently.

For reference, the other two attempts were #4201 and #4280.

This series tries to mimic what the Intel driver is doing, and will try to use the RGB format first, and if we're above our clock limits will try again using YUV422. If both fails, we'll reject the commit entirely.

This is based on 5.15, let me know if you would prefer a branch based on 5.10. I also plan on sending it today upstream to start the discussion and see if it gets more traction than the other attempts.

Maxime

@popcornmix
Copy link
Collaborator

Before this PR:

pi@pi4:~ $ modetest -M vc4 -v -w  "32:max bpc:8" -F tiles,gradient -s 32:3840x2160-60 -P91@76:3840x2160+0+0@XR24
setting mode 3840x2160-60.00Hz on connectors 32, crtc 76
testing 3840x2160@XR24 overlay plane 91
freq: 60.18Hz
freq: 60.00Hz

after this PR:

pi@pi4:~ $ modetest -M vc4 -v -w  "32:max bpc:8" -F tiles,gradient -s 32:3840x2160-60 -P91@76:3840x2160+0+0@XR24
setting mode 3840x2160-60.00Hz on connectors 32, crtc 76
testing 3840x2160@XR24 overlay plane 91
freq: 5.80Hz
freq: 5.77Hz

Something has gone wrong with the fps timing.

@popcornmix
Copy link
Collaborator

On LibreELEC modetest is behaving more sensibly but:

LibreELEC4:~ # modetest -M vc4 -v -w  "32:max bpc:12" -F tiles,gradient -s 32:3840x2160-60 -P91@76:3840x2160+0+0@XR24
setting mode 3840x2160-60.00Hz on connectors 32, crtc 76
testing 3840x2160@XR24 overlay plane 91
freq: 40.51Hz
freq: 40.00Hz

So we are getting 4kp40 when requesting 12-bit 4kp60, so there is an issue with clocks.

@popcornmix
Copy link
Collaborator

I think we need this logic for clocks:

if (BIT(conn_state->color_format) == DRM_COLOR_FORMAT_RGB444 ||
BIT(conn_state->color_format) == DRM_COLOR_FORMAT_YCRCB444) {
if (conn_state->max_bpc == 12) {
pixel_rate = pixel_rate * 150;
do_div(pixel_rate, 100);
} else if (conn_state->max_bpc == 10) {
pixel_rate = pixel_rate * 125;
do_div(pixel_rate, 100);
}
}

@HiassofT
Copy link
Contributor

HiassofT commented Dec 3, 2021

As discussed on Slack there are some more things we need to concern:

  • We should only use YCbCr if an HDMI monitor is connected and support for YCbCr 4:2:2 (or 4:4:4, respectively) is indicated in the CTA extension block of the EDID (see CTA-861-G section 5.1) - otherwise we'll break compatibility with DVI monitors which only accept RGB
  • YCbCr 4:2:2 is a 36-bit mode (12-bit per component) and we should not use that with 8 or 10 bits, only 12-bit (HDMI 1.4b section 6.2.4)
  • 640x480 should only be using 8-bit mode (CTA-861-G section 5.4)
  • RGB or YCbCr 4:4:4 10/12-bit deep color modes should only be used if support is indicated in the EDID in the HDMI VSDB (DC_30bit/DC_36bit/DC_Y444 flags - see HDMI 1.4b section 8.3.2)

@@ -1065,6 +1067,12 @@ static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
break;
}

// YCC422 is always 36-bit and not considered deep colour so doesn't signal in GCP
if (vc4_state->output_format == DRM_COLOR_FORMAT_YCRCB422) {
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Should this be VC4_HDMI_OUTPUT_YUV422?

{
unsigned long clock = mode->crtc_clock * 1000;

if (mode->flags & DRM_MODE_FLAG_DBLCLK)
clock = clock * 2;

if (fmt == VC4_HDMI_OUTPUT_YUV422)
clock = clock * 2 / 3;
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think you want bcp=8 instead. The clock rate does not change in YCC422 modes. The bpc does not affect clock rate.

@popcornmix
Copy link
Collaborator

With the two fixes I suggested,

modetest -M vc4 -v -w  "32:max bpc:8" -F tiles,gradient -s 32:3840x2160-60 -P91@76:3840x2160+0+0@XR24
modetest -M vc4 -v -w  "32:max bpc:10" -F tiles,gradient -s 32:3840x2160-60 -P91@76:3840x2160+0+0@XR24
modetest -M vc4 -v -w  "32:max bpc:12" -F tiles,gradient -s 32:3840x2160-60 -P91@76:3840x2160+0+0@XR24

all report 60fps (at least from a LibreELEC build). Without the changes the framerate lowers as bpc increases.

@popcornmix
Copy link
Collaborator

Testing more with modetest:
4kp24/4kp25/4kp30/4kp50/4kp60 at 8bit working
4kp50/4kp60 at 10bit or 12bit working
4kp24/4kp25/4kp30 at 10bit or 12bit NOT working (modetest reports right framerate, but nothing on display)

1080p24/1080p25/1080p30/1080p50/1080p60 at 8bit or 10bit or 12bit working

@popcornmix
Copy link
Collaborator

modetest with 4kp30 reports:

[ 2306.530795] vc4-drm gpu: [drm:vc4_hdmi_encoder_atomic_check] Trying to output in RGB, with 12 bpp
[ 2306.530813] vc4-drm gpu: [drm:vc4_hdmi_encoder_atomic_check] Failed. Trying in YUV422, with 12 bpp

which is surprising as I'd expect 4kp30 to be 297MHz for 8bit (and 297MHz * 1.5 for RGB) and so RGB should pass.
But when I add logging,

[ 2306.530804] vc4-drm gpu: [drm:vc4_hdmi_encoder_compute_clock] fmt:0 bpc:12 clock:891000000 mode:3840x2160:594000,3840x2160
[ 2306.530819] vc4-drm gpu: [drm:vc4_hdmi_encoder_compute_clock] fmt:1 bpc:12 clock:594000000 mode:3840x2160:594000,3840x2160

mode->clock is 594MHz (e.g. 4kp60) rather than 297MHz I am expecting. Any idea why?

@mripard
Copy link
Contributor Author

mripard commented Dec 10, 2021

I've reworked the current code and get a sane clock now for 4k at 30Hz, however, it won't enable the scrambler since we only check on the timings clock and don't take the bpc and format into account. I'll work on that.

@popcornmix
Copy link
Collaborator

Sounds good. That was going to be my next question.
Chatting with @timg236 we noticed 12-bit RGB 4kp30 needs scrambling where 8-bit RGB 4kp30 doesn't.
But it sounds like you are already on that.

@mripard
Copy link
Contributor Author

mripard commented Dec 10, 2021

I've just pushed a new version that should address most of the issues raised so far.

The one thing I haven't been able to fix yet is that, even though my monitor reports that it supports YUV422, it looks like the drm_display_info structure doesn't have the matching bit set and thus we always ignore it.

@popcornmix
Copy link
Collaborator

I get the same issue

modetest -M vc4 -v -w 32:max bpc:12 -F tiles,gradient -s 32:3840x2160-60 -P91@76:3840x2160+0+0@XR24

results in:

[  798.098074] vc4-drm gpu: [drm:vc4_hdmi_encoder_atomic_check] Sink doesn't support YUV422.

But the display does support this (and was outputting it with your previous version of this PR).

Also the update means we default to 12bpc by default (previous version was 8bpc).
So console and desktop try to output 12bpc 4kp60.
Which if 422 was working would result in 12bpc YCC422 4kp60 without needing it.
That will be lower quality than 8bpc RGB444 4kp60, as we are gaining nothing from the extra bpc
(the framebuffer is only 8bpc), but we lose some chroma resolution from the YCC422 output.

It also means, for, say 1080p60 we will output 12bpc and have 50% higher clocks, which could result in complaints from users with less than ideal HDMI cables.

I was hoping that we would default to 8bpc, and only switch to 12bpc if the user application sets the "max bpc" to 12. That can only be done when required - e.g. with a 10bpc (P030) video playing.
The previous version of this PR behaved in that way.

@HiassofT
Copy link
Contributor

Just spotted another issue: vc4_hdmi_encoder_clock_valid (or some other code parts) should check if a HDMI VSDB is present in EDID and if yes cap the clock at the TMDS limit - see HDMI 1.4b section 8.3

The Source shall not transmit at TMDS clock rates higher than the maximum rate supported by the
Sink, as determined by video format and Deep Color mode support indications but limited by the
Max_TMDS_Clock field of the HDMI VSDB.

It might make sense to simply skip this check at 8bpc as I've seen EDIDs with nonsense or no values in there - as we'd do for DVI devices (which usually don't report an HDMI VSDB)

@HiassofT
Copy link
Contributor

Ah, drm_display_info already has parsed max_tmds_clock, so I'd suggest doing the capping like in the intel driver https://github.com/raspberrypi/linux/blob/rpi-5.15.y/drivers/gpu/drm/i915/display/intel_hdmi.c#L1818-L1820

@HiassofT
Copy link
Contributor

Quick heads up, there's a bug in drm_edid.c's deep color parsing function, it incorrectly removes YCRCB422:
https://github.com/raspberrypi/linux/blob/rpi-5.15.y/drivers/gpu/drm/drm_edid.c#L5035-L5040

	/*
	 * Deep color support mandates RGB444 support for all video
	 * modes and forbids YCRCB422 support for all video modes per
	 * HDMI 1.3 spec.
	 */
	info->color_formats = DRM_COLOR_FORMAT_RGB444;

HDMI 1.3 (section 6.2.4) doesn't state that YCRCB422 isn't allowed at all if a sink supports deep color, only that this is not a valid deep color mode
| YCBCR 4:2:2 is not permitted for any Deep Color mode.

HDMI 1.4 (section 6.2.4) clarifies this further
| YCBCR 4:2:2 is also 36-bit mode but does not require the further use of the Deep Color modes described in section 6.5.2 and 6.5.3.

@popcornmix
Copy link
Collaborator

@HiassofT so the line should be:

info->color_formats |= DRM_COLOR_FORMAT_RGB444;

?

@mripard mripard force-pushed the rpi/hdmi-yuv-simpler branch from b56ce77 to 88471fd Compare December 13, 2021 14:56
@mripard
Copy link
Contributor Author

mripard commented Dec 13, 2021

I've pushed a version fixing the YUV422 issue like @HiassofT suggested, took the max_tmds_clock into account and dropped the part raising the default max_bpc property

@HiassofT
Copy link
Contributor

@popcornmix yes, that's fine

DRM_COLOR_FORMAT_RGB444 will already be set if a CEA extension block is found https://github.com/raspberrypi/linux/blob/rpi-5.15.y/drivers/gpu/drm/drm_edid.c#L5093-L5094

so while it's not strictly necessary to add it again it's more readable and safer if we explicitly enable it here

@popcornmix
Copy link
Collaborator

Functionally this is looking good. I seem to be getting the expected output formats and clocks for a wide range of resolution/bpc/framerate.

But LE is starting up with a blank screen: when run without hdmi_enable_4kp60=1.
I can use modetest to switch to other resolutions okay. Adding that line boots and displays okay.
Anything suspicious in dmesg log or modetest or /sys/kernel/debug/dri/0/state?

@popcornmix
Copy link
Collaborator

So the place where the blank screen diverges is:
(with hdmi_enable_4kp60=1)

[drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:TMDS-31] to (____ptrval____)
vc4-drm gpu: [drm:vc4_hdmi_encoder_atomic_check] Trying with a 8 bpc output
vc4-drm gpu: [drm:vc4_hdmi_encoder_atomic_check] Trying with an RGB output
vc4-drm gpu: [drm:vc4_hdmi_encoder_atomic_check] RGB Format, checking the constraints.
vc4-drm gpu: [drm:vc4_hdmi_encoder_atomic_check] RGB format supported in that configuration.
vc4-drm gpu: [drm:vc4_hdmi_encoder_atomic_check] Mode 3840x2160 @ 60Hz: Found configuration: bpc: 8, fmt: RGB, clock: 594000000

(without hdmi_enable_4kp60=1)

[drm:drm_atomic_add_encoder_bridges] Adding all bridges for [encoder:31:TMDS-31] to (____ptrval____)
[drm:drm_atomic_helper_check_modeset] [ENCODER:31:TMDS-31] mode_valid() failed
[drm:drm_atomic_check_only] atomic driver check for (____ptrval____) failed: -22

if (mode->flags & DRM_MODE_FLAG_DBLCLK)
clock = clock * 2;

return clock * bpc / 8;
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This overflows resulting in scrambling not getting enabled. (e.g. clock=594000000 bpc=8)
Need something like return (u64)clock * bpc / 8

@mripard mripard force-pushed the rpi/hdmi-yuv-simpler branch from 88471fd to 694813e Compare December 15, 2021 10:44
@mripard
Copy link
Contributor Author

mripard commented Dec 15, 2021

Indeed, thanks for the report. I've fixed it by using an unsigned long long everywhere for the clock since it's what we were using in the vc4_hdmi_connector_state to store it anyway.

return MODE_CLOCK_HIGH;

return MODE_OK;
return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->crtc_clock * 1000);
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This should be mode->clock not mode->crtc_clock.
It's the cause of blank screen when booting LE at 4kp30.
Logging shows mode->clock is set to plausible value but mode->crtc_clock is often 0 here.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Indeed, it's filled by drm_mode_set_crtcinfo() which is called right after .mode_valid. I've fixed it.

@mripard mripard force-pushed the rpi/hdmi-yuv-simpler branch from 694813e to ad829ab Compare December 16, 2021 08:44
The current code, when parsing the EDID Deep Color depths, that the
YUV422 cannot be used, referring to the HDMI 1.3 Specification.

This specification, in its section 6.2.4, indeed states:

  For each supported Deep Color mode, RGB 4:4:4 shall be supported and
  optionally YCBCR 4:4:4 may be supported.

  YCBCR 4:2:2 is not permitted for any Deep Color mode.

This indeed can be interpreted like the code does, but the HDMI 1.4
specification further clarifies that statement in its section 6.2.4:

  For each supported Deep Color mode, RGB 4:4:4 shall be supported and
  optionally YCBCR 4:4:4 may be supported.

  YCBCR 4:2:2 is also 36-bit mode but does not require the further use
  of the Deep Color modes described in section 6.5.2 and 6.5.3.

This means that, even though YUV422 can be used with 12 bit per color,
it shouldn't be treated as a deep color mode.

This deviates from the interpretation of the code and comment, so let's
fix those.

Fixes: d0c9469 ("drm/edid: Parse and handle HDMI deep color modes.")
Signed-off-by: Maxime Ripard <[email protected]>
The drm_hdmi_avi_infoframe_colorspace() function actually sets the
colorimetry and extended_colorimetry fields in the hdmi_avi_infoframe
structure with DRM_MODE_COLORIMETRY_* values.

To make things worse, the hdmi_avi_infoframe structure also has a
colorspace field used to signal whether an RGB or YUV output is being
used.

Let's remove the inconsistency and allow for the colorspace usage by
renaming the function.

Signed-off-by: Maxime Ripard <[email protected]>
We're going to need to tell whether we want to run with a full or
limited range RGB output in multiple places in the code, so let's create
a helper that will return whether we need with full range or not.

Acked-by: Thomas Zimmermann <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
The CSC callbacks takes a boolean as an argument to tell whether we're
using the full range or limited range RGB.

However, with the upcoming YUV support, the logic will be a bit more
complex. In order to address this, let's make the callbacks take the
entire mode, and call our new helper to tell whether the full or limited
range RGB should be used.

Acked-by: Thomas Zimmermann <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
On the BCM2711, the HDMI_VEC_INTERFACE_XBAR register configuration
depends on whether we're using an RGB or YUV output. Let's move that
configuration to the CSC setup.

Acked-by: Thomas Zimmermann <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
On BCM2711, the HDMI_CSC_CTL register value has been hardcoded to an
opaque value. Let's replace it with properly defined values.

Acked-by: Thomas Zimmermann <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
The current CSC setup code for the BCM2711 uses a sequence of register
writes to configure the CSC depending on whether we output using a full
or limited range.

However, with the upcoming introduction of the YUV output, we're going
to add new matrices to perform the conversions, so we should switch to
something a bit more flexible that takes the matrix as an argument and
programs the CSC accordingly.

Acked-by: Thomas Zimmermann <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
In order to support the YUV output, we'll need the atomic state to know
what is the state of the associated property in the CSC setup callback.

Let's change the prototype of that callback to allow us to access it.

Acked-by: Thomas Zimmermann <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>
Our code is doing the same clock rate validation in multiple instances.
Let's create a helper to share the rate validation.

Signed-off-by: Maxime Ripard <[email protected]>
The code to compute our clock rate for a given setup will be called in
multiple places in the next patches, so let's create a separate function
for it.

Signed-off-by: Maxime Ripard <[email protected]>
In the function that validates that the clock isn't too high, we've only
taken our controller limitations into account so far.

However, the sink can have a limit on the maximum TMDS clock it can deal
with too which is exposed through the EDID and the drm_display_info.

Make sure we check it.

Signed-off-by: Maxime Ripard <[email protected]>
The current code only base its decision for whether the scrambler must be
enabled or not on the pixel clock of the mode, but doesn't take the bits
per color into account.

Let's leverage the new function to compute the clock rate in the
scrambler setup code.

Signed-off-by: Maxime Ripard <[email protected]>
Currently we take the max_bpc property as the bpc value and do not try
anything else.

However, what the other drivers seem to be doing is that they would try
with the highest bpc allowed by the max_bpc property and the hardware
capabilities, test if it results in an acceptable configuration, and if
not decrease the bpc and try again.

Let's use the same logic.

Signed-off-by: Maxime Ripard <[email protected]>
In addition to the RGB444 output, the BCM2711 HDMI controller supports
the YUV444 and YUV422 output formats.

Let's add support for them in the driver, but still use RGB as the
preferred format.

Signed-off-by: Maxime Ripard <[email protected]>
@mripard mripard force-pushed the rpi/hdmi-yuv-simpler branch from ad829ab to daeede0 Compare December 16, 2021 17:43
@popcornmix
Copy link
Collaborator

I'm happy with this after quite a lot of testing. Also tested by @HiassofT.

@pelwell pelwell merged commit de34dbf into raspberrypi:rpi-5.15.y Dec 17, 2021
@pelwell
Copy link
Contributor

pelwell commented Dec 17, 2021

I get no display with these commits:

[   18.599563] ------------[ cut here ]------------
[   18.599576] WARNING: CPU: 1 PID: 684 at drivers/gpu/drm/vc4/vc4_hdmi.c:481 vc4_hdmi_write_infoframe+0x388/0x700 [vc4]
[   18.599664] Packet RAM has to be on to store the packet.
[   18.599670] Modules linked in: aes_arm_bs crypto_simd cryptd algif_skcipher af_alg bnep hci_uart btbcm bluetooth ecdh_generic ecc 8021q garp stp llc snd_soc_hdmi_codec brcmfmac brcmutil v3d cfg80211 rfkill gpu_sched raspberrypi_hwmon vc4 bcm2835_v4l2(C) bcm2835_isp(C) bcm2835_codec(C) bcm2835_mmal_vchiq(C) v4l2_mem2mem cec videobuf2_vmalloc drm_kms_helper videobuf2_dma_contig i2c_brcmstb snd_soc_core videobuf2_memops videobuf2_v4l2 snd_compress videobuf2_common snd_bcm2835(C) snd_pcm_dmaengine videodev vc_sm_cma(C) mc snd_pcm snd_timer rpivid_mem snd syscopyarea sysfillrect sysimgblt fb_sys_fops nvmem_rmem uio_pdrv_genirq uio i2c_dev fuse drm drm_panel_orientation_quirks backlight ip_tables x_tables ipv6
[   18.600062] CPU: 1 PID: 684 Comm: pulseaudio Tainted: G         C        5.15.8-v7l+ #1890
[   18.600070] Hardware name: BCM2711
[   18.600074] Backtrace:
[   18.600080] [<c0bdf6e0>] (dump_backtrace) from [<c0bdf928>] (show_stack+0x20/0x24)
[   18.600100]  r7:000001e1 r6:00000000 r5:c0e3cc78 r4:60000013
[   18.600103] [<c0bdf908>] (show_stack) from [<c0be3fd4>] (dump_stack_lvl+0x70/0x94)
[   18.600115] [<c0be3f64>] (dump_stack_lvl) from [<c0be4010>] (dump_stack+0x18/0x1c)
[   18.600127]  r7:000001e1 r6:bf3adf18 r5:00000009 r4:bf3c84d4
[   18.600130] [<c0be3ff8>] (dump_stack) from [<c02212ec>] (__warn+0xfc/0x114)
[   18.600141] [<c02211f0>] (__warn) from [<c0be002c>] (warn_slowpath_fmt+0xa8/0xe8)
[   18.600152]  r7:bf3adf18 r6:000001e1 r5:bf3c84d4 r4:bf3c864c
[   18.600155] [<c0bdff88>] (warn_slowpath_fmt) from [<bf3adf18>] (vc4_hdmi_write_infoframe+0x388/0x700 [vc4])
[   18.600227]  r8:00000084 r7:00000000 r6:c37b7c38 r5:f0877b00 r4:c2fdc2a0
[   18.600231] [<bf3adb90>] (vc4_hdmi_write_infoframe [vc4]) from [<bf3aea70>] (vc4_hdmi_audio_prepare+0x7e0/0xd2c [vc4])
[   18.600348]  r10:c2fdc77c r9:00000000 r8:bf3c36b8 r7:c37b7cbc r6:bf3c36b8 r5:c2fdc040
[   18.600352]  r4:00000000
[   18.600355] [<bf3ae290>] (vc4_hdmi_audio_prepare [vc4]) from [<bf20a9d0>] (hdmi_codec_prepare+0xe8/0x130 [snd_soc_hdmi_codec])
[   18.600424]  r10:c2975cd0 r9:c37b7cbc r8:c3567880 r7:c2ee8e40 r6:c29a8000 r5:c2890d00
[   18.600428]  r4:bf3ae290
[   18.600431] [<bf20a8e8>] (hdmi_codec_prepare [snd_soc_hdmi_codec]) from [<bf2d222c>] (snd_soc_pcm_dai_prepare+0x54/0xc4 [snd_soc_core])
[   18.600522]  r9:00000000 r8:c3f531c0 r7:c2a88100 r6:c2fdd040 r5:00000001 r4:c2890d00
[   18.600526] [<bf2d21d8>] (snd_soc_pcm_dai_prepare [snd_soc_core]) from [<bf2d5dd8>] (soc_pcm_prepare+0x50/0x120 [snd_soc_core])
[   18.600662]  r9:00000000 r8:c3f531c0 r7:c2a88100 r6:00000000 r5:00000802 r4:c2fdd040
[   18.600665] [<bf2d5d88>] (soc_pcm_prepare [snd_soc_core]) from [<bf1d65f0>] (snd_pcm_do_prepare+0x34/0x4c [snd_pcm])
[   18.600771]  r7:00000802 r6:c2a88100 r5:00000802 r4:c2a88100
...

@pelwell
Copy link
Contributor

pelwell commented Dec 17, 2021

PR reverted for now.

@popcornmix
Copy link
Collaborator

I believe that warn is due to the lack of #4770

@pelwell
Copy link
Contributor

pelwell commented Dec 17, 2021

For me, with #4770 cherry-picked I still see no display output. Reverting d379321 restores it.

@pelwell
Copy link
Contributor

pelwell commented Dec 17, 2021

edid-decode (hex):

00 ff ff ff ff ff ff 00 09 d1 ce 78 45 54 00 00
03 18 01 03 80 35 1e 78 2e 6b 35 a4 55 55 9f 27
0c 50 54 a5 6b 80 d1 c0 81 c0 81 00 81 80 a9 c0
b3 00 01 01 01 01 02 3a 80 18 71 38 2d 40 58 2c
45 00 13 2b 21 00 00 1e 00 00 00 ff 00 4e 31 45
30 34 38 31 39 53 4c 30 0a 20 00 00 00 fd 00 32
4c 1e 53 11 00 0a 20 20 20 20 20 20 00 00 00 fc
00 42 65 6e 51 20 47 4c 32 34 36 30 0a 20 01 88

02 03 22 f1 4f 90 05 04 03 02 01 11 12 13 14 06
07 15 16 1f 23 09 07 07 65 03 0c 00 10 00 83 01
00 00 02 3a 80 18 71 38 2d 40 58 2c 45 00 13 2b
21 00 00 1f 01 1d 80 18 71 1c 16 20 58 2c 25 00
13 2b 21 00 00 9f 01 1d 00 72 51 d0 1e 20 6e 28
55 00 13 2b 21 00 00 1e 8c 0a d0 8a 20 e0 2d 10
10 3e 96 00 13 2b 21 00 00 18 00 00 00 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e7

----------------

Block 0, Base EDID:
  EDID Structure Version & Revision: 1.3
  Vendor & Product Identification:
    Manufacturer: BNQ
    Model: 30926
    Serial Number: 21573
    Made in: week 3 of 2014
  Basic Display Parameters & Features:
    Digital display
    Maximum image size: 53 cm x 30 cm
    Gamma: 2.20
    DPMS levels: Off
    RGB color display
    Default (sRGB) color space is primary color space
    First detailed timing is the preferred timing
  Color Characteristics:
    Red  : 0.6416, 0.3339
    Green: 0.3339, 0.6240
    Blue : 0.1523, 0.0498
    White: 0.3134, 0.3291
  Established Timings I & II:
    IBM     :   720x400    70.082 Hz   9:5    31.467 kHz  28.320 MHz
    DMT 0x04:   640x480    59.940 Hz   4:3    31.469 kHz  25.175 MHz
    DMT 0x06:   640x480    75.000 Hz   4:3    37.500 kHz  31.500 MHz
    DMT 0x09:   800x600    60.317 Hz   4:3    37.879 kHz  40.000 MHz
    DMT 0x0b:   800x600    75.000 Hz   4:3    46.875 kHz  49.500 MHz
    Apple   :   832x624    74.551 Hz   4:3    49.726 kHz  57.284 MHz
    DMT 0x10:  1024x768    60.004 Hz   4:3    48.363 kHz  65.000 MHz
    DMT 0x12:  1024x768    75.029 Hz   4:3    60.023 kHz  78.750 MHz
    DMT 0x24:  1280x1024   75.025 Hz   5:4    79.976 kHz 135.000 MHz
    Apple   :  1152x870    75.062 Hz 192:145  68.681 kHz 100.000 MHz
  Standard Timings:
    DMT 0x52:  1920x1080   60.000 Hz  16:9    67.500 kHz 148.500 MHz
    DMT 0x55:  1280x720    60.000 Hz  16:9    45.000 kHz  74.250 MHz
    DMT 0x1c:  1280x800    59.810 Hz  16:10   49.702 kHz  83.500 MHz
    DMT 0x23:  1280x1024   60.020 Hz   5:4    63.981 kHz 108.000 MHz
    DMT 0x53:  1600x900    60.000 Hz  16:9    60.000 kHz 108.000 MHz (RB)
    DMT 0x3a:  1680x1050   59.954 Hz  16:10   65.290 kHz 146.250 MHz
  Detailed Timing Descriptors:
    DTD 1:  1920x1080   60.000 Hz  16:9    67.500 kHz 148.500 MHz (531 mm x 299 mm)
                 Hfront   88 Hsync  44 Hback 148 Hpol P
                 Vfront    4 Vsync   5 Vback  36 Vpol P
    Display Product Serial Number: 'N1E04819SL0'
  Display Range Limits:
    Monitor ranges (GTF): 50-76 Hz V, 30-83 kHz H, max dotclock 170 MHz
    Display Product Name: 'BenQ GL2460'
  Extension blocks: 1
Checksum: 0x88

----------------

Block 1, CTA-861 Extension Block:
  Revision: 3
  Underscans IT Video Formats by default
  Basic audio support
  Supports YCbCr 4:4:4
  Supports YCbCr 4:2:2
  Native detailed modes: 1
  Video Data Block:
    VIC  16:  1920x1080   60.000 Hz  16:9    67.500 kHz 148.500 MHz (native)
    VIC   5:  1920x1080i  60.000 Hz  16:9    33.750 kHz  74.250 MHz
    VIC   4:  1280x720    60.000 Hz  16:9    45.000 kHz  74.250 MHz
    VIC   3:   720x480    59.940 Hz  16:9    31.469 kHz  27.000 MHz
    VIC   2:   720x480    59.940 Hz   4:3    31.469 kHz  27.000 MHz
    VIC   1:   640x480    59.940 Hz   4:3    31.469 kHz  25.175 MHz
    VIC  17:   720x576    50.000 Hz   4:3    31.250 kHz  27.000 MHz
    VIC  18:   720x576    50.000 Hz  16:9    31.250 kHz  27.000 MHz
    VIC  19:  1280x720    50.000 Hz  16:9    37.500 kHz  74.250 MHz
    VIC  20:  1920x1080i  50.000 Hz  16:9    28.125 kHz  74.250 MHz
    VIC   6:  1440x480i   59.940 Hz   4:3    15.734 kHz  27.000 MHz
    VIC   7:  1440x480i   59.940 Hz  16:9    15.734 kHz  27.000 MHz
    VIC  21:  1440x576i   50.000 Hz   4:3    15.625 kHz  27.000 MHz
    VIC  22:  1440x576i   50.000 Hz  16:9    15.625 kHz  27.000 MHz
    VIC  31:  1920x1080   50.000 Hz  16:9    56.250 kHz 148.500 MHz
  Audio Data Block:
    Linear PCM:
      Max channels: 2
      Supported sample rates (kHz): 48 44.1 32
      Supported sample sizes (bits): 24 20 16
  Vendor-Specific Data Block (HDMI), OUI 00-0C-03:
    Source physical address: 1.0.0.0
  Speaker Allocation Data Block:
    FL/FR - Front Left/Right
  Detailed Timing Descriptors:
    DTD 2:  1920x1080   60.000 Hz  16:9    67.500 kHz 148.500 MHz (531 mm x 299 mm)
                 Hfront   88 Hsync  44 Hback 148 Hpol P
                 Vfront    4 Vsync   5 Vback  36 Vpol P
    DTD 3:  1920x1080i  60.000 Hz  16:9    33.750 kHz  74.250 MHz (531 mm x 299 mm)
                 Hfront   88 Hsync  44 Hback 148 Hpol P
                 Vfront    2 Vsync   5 Vback  15 Vpol P Vfront +0.5 Odd Field
                 Vfront    2 Vsync   5 Vback  15 Vpol P Vback  +0.5 Even Field
    DTD 4:  1280x720    60.000 Hz  16:9    45.000 kHz  74.250 MHz (531 mm x 299 mm)
                 Hfront  110 Hsync  40 Hback 220 Hpol P
                 Vfront    5 Vsync   5 Vback  20 Vpol P
    DTD 5:   720x480    59.940 Hz   3:2    31.469 kHz  27.000 MHz (531 mm x 299 mm)
                 Hfront   16 Hsync  62 Hback  60 Hpol N
                 Vfront    9 Vsync   6 Vback  30 Vpol N
Checksum: 0xe7

@popcornmix
Copy link
Collaborator

popcornmix commented Dec 17, 2021

I think

	if (clock > (info->max_tmds_clock * 1000))
		return MODE_CLOCK_HIGH;

should be

	if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
		return MODE_CLOCK_HIGH;

as the max_tmds_clock looks to be optional in edid.
meson_dw_hdmi.c has similar logic. And radeon

@pelwell
Copy link
Contributor

pelwell commented Dec 17, 2021

I agree - max_tmds_clock is 0 with this monitor.

@pelwell
Copy link
Contributor

pelwell commented Dec 17, 2021

Reapplied with the fix included.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

4 participants