[Asan] Provide TTI hook to provide memory reference infromation of target intrinsics. #97070
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@llvm/pr-subscribers-llvm-transforms @llvm/pr-subscribers-compiler-rt-sanitizer Author: Yeting Kuo (yetingk) ChangesPreviously asan considers target intrinsics as black boxes, so asan could not instrument accurate check. This patch provide TTI hooks to make targets describe their intrinsic informations to asan. Note,
Patch is 1.23 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/97070.diff 11 Files Affected:
diff --git a/llvm/include/llvm/Analysis/MemoryRefInfo.h b/llvm/include/llvm/Analysis/MemoryRefInfo.h
new file mode 100644
index 0000000000000..4621f94f6b16c
--- /dev/null
+++ b/llvm/include/llvm/Analysis/MemoryRefInfo.h
@@ -0,0 +1,52 @@
+//===--------- Definition of the MemoryRefInfo class -*- C++ -*------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines MemoryRefInfo class that is used when getting
+// the information of a memory reference instruction.
+//
+//===----------------------------------------------------------------------===//
+#ifndef LLVM_SUPPORT_MEMORYREFINFO_H
+#define LLVM_SUPPORT_MEMORYREFINFO_H
+
+#include "llvm/IR/Instruction.h"
+#include "llvm/Support/TypeSize.h"
+
+namespace llvm {
+class MemoryRefInfo {
+public:
+ Use *PtrUse = nullptr;
+ bool IsWrite;
+ Type *OpType;
+ TypeSize TypeStoreSize = TypeSize::getFixed(0);
+ MaybeAlign Alignment;
+ // The mask Value, if we're looking at a masked load/store.
+ Value *MaybeMask;
+ // The EVL Value, if we're looking at a vp intrinsic.
+ Value *MaybeEVL;
+ // The Stride Value, if we're looking at a strided load/store.
+ Value *MaybeStride;
+
+ MemoryRefInfo() = default;
+ MemoryRefInfo(Instruction *I, unsigned OperandNo, bool IsWrite,
+ class Type *OpType, MaybeAlign Alignment,
+ Value *MaybeMask = nullptr, Value *MaybeEVL = nullptr,
+ Value *MaybeStride = nullptr)
+ : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment),
+ MaybeMask(MaybeMask), MaybeEVL(MaybeEVL), MaybeStride(MaybeStride) {
+ const DataLayout &DL = I->getDataLayout();
+ TypeStoreSize = DL.getTypeStoreSizeInBits(OpType);
+ PtrUse = &I->getOperandUse(OperandNo);
+ }
+
+ Instruction *getInsn() { return cast<Instruction>(PtrUse->getUser()); }
+ Value *getPtr() { return PtrUse->get(); }
+ operator bool() { return PtrUse != nullptr; }
+};
+
+} // namespace llvm
+#endif
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h
index dcdd9f82cde8e..3a27e8c9263d4 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfo.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h
@@ -23,6 +23,7 @@
#include "llvm/ADT/APInt.h"
#include "llvm/ADT/SmallBitVector.h"
+#include "llvm/Analysis/MemoryRefInfo.h"
#include "llvm/IR/FMF.h"
#include "llvm/IR/InstrTypes.h"
#include "llvm/IR/PassManager.h"
@@ -955,6 +956,10 @@ class TargetTransformInfo {
MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
bool IsZeroCmp) const;
+ // Add MemoryRefInfo of Intrinsic \p II into array \p Interesting.
+ bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const;
+
/// Should the Select Optimization pass be enabled and ran.
bool enableSelectOptimize() const;
@@ -1932,6 +1937,8 @@ class TargetTransformInfo::Concept {
virtual bool enableAggressiveInterleaving(bool LoopHasReductions) = 0;
virtual MemCmpExpansionOptions
enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const = 0;
+ virtual bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const = 0;
virtual bool enableSelectOptimize() = 0;
virtual bool shouldTreatInstructionLikeSelect(const Instruction *I) = 0;
virtual bool enableInterleavedAccessVectorization() = 0;
@@ -2485,6 +2492,12 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
bool IsZeroCmp) const override {
return Impl.enableMemCmpExpansion(OptSize, IsZeroCmp);
}
+
+ bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const override {
+ return Impl.getMemoryRefInfo(Interesting, II);
+ }
+
bool enableSelectOptimize() override {
return Impl.enableSelectOptimize();
}
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 0ded98f162abf..c46bd480aa3b3 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -394,6 +394,11 @@ class TargetTransformInfoImplBase {
return {};
}
+ bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const {
+ return false;
+ }
+
bool enableSelectOptimize() const { return true; }
bool shouldTreatInstructionLikeSelect(const Instruction *I) {
diff --git a/llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h b/llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
index 9fe2716220e83..f7bd36c2def03 100644
--- a/llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
+++ b/llvm/include/llvm/Transforms/Instrumentation/AddressSanitizerCommon.h
@@ -14,6 +14,7 @@
#define LLVM_TRANSFORMS_INSTRUMENTATION_ADDRESSSANITIZERCOMMON_H
#include "llvm/Analysis/CFG.h"
+#include "llvm/Analysis/MemoryRefInfo.h"
#include "llvm/Analysis/PostDominators.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/Instruction.h"
@@ -22,37 +23,6 @@
namespace llvm {
-class InterestingMemoryOperand {
-public:
- Use *PtrUse;
- bool IsWrite;
- Type *OpType;
- TypeSize TypeStoreSize = TypeSize::getFixed(0);
- MaybeAlign Alignment;
- // The mask Value, if we're looking at a masked load/store.
- Value *MaybeMask;
- // The EVL Value, if we're looking at a vp intrinsic.
- Value *MaybeEVL;
- // The Stride Value, if we're looking at a strided load/store.
- Value *MaybeStride;
-
- InterestingMemoryOperand(Instruction *I, unsigned OperandNo, bool IsWrite,
- class Type *OpType, MaybeAlign Alignment,
- Value *MaybeMask = nullptr,
- Value *MaybeEVL = nullptr,
- Value *MaybeStride = nullptr)
- : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment),
- MaybeMask(MaybeMask), MaybeEVL(MaybeEVL), MaybeStride(MaybeStride) {
- const DataLayout &DL = I->getDataLayout();
- TypeStoreSize = DL.getTypeStoreSizeInBits(OpType);
- PtrUse = &I->getOperandUse(OperandNo);
- }
-
- Instruction *getInsn() { return cast<Instruction>(PtrUse->getUser()); }
-
- Value *getPtr() { return PtrUse->get(); }
-};
-
// Get AddressSanitizer parameters.
void getAddressSanitizerParams(const Triple &TargetTriple, int LongSize,
bool IsKasan, uint64_t *ShadowBase,
diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp
index c175d1737e54b..3b89e74f5b4ae 100644
--- a/llvm/lib/Analysis/TargetTransformInfo.cpp
+++ b/llvm/lib/Analysis/TargetTransformInfo.cpp
@@ -622,6 +622,11 @@ TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
}
+bool TargetTransformInfo::getMemoryRefInfo(
+ SmallVectorImpl<MemoryRefInfo> &Interesting, IntrinsicInst *II) const {
+ return TTIImpl->getMemoryRefInfo(Interesting, II);
+}
+
bool TargetTransformInfo::enableSelectOptimize() const {
return TTIImpl->enableSelectOptimize();
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index 176d0e79253ac..d87f9f8b5f0de 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -13,7 +13,9 @@
#include "llvm/CodeGen/BasicTTIImpl.h"
#include "llvm/CodeGen/CostTable.h"
#include "llvm/CodeGen/TargetLowering.h"
+#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/Instructions.h"
+#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
#include <cmath>
#include <optional>
@@ -36,6 +38,91 @@ static cl::opt<unsigned> SLPMaxVF(
"exclusively by SLP vectorizer."),
cl::Hidden);
+bool RISCVTTIImpl::getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const {
+ const DataLayout &DL = getDataLayout();
+ unsigned IntNo = II->getIntrinsicID();
+ LLVMContext &C = II->getContext();
+ IRBuilder<> IB(II);
+ bool HasMask = false;
+
+ switch (IntNo) {
+ case Intrinsic::riscv_vle_mask:
+ case Intrinsic::riscv_vse_mask:
+ HasMask = true;
+ [[fallthrough]];
+ case Intrinsic::riscv_vle:
+ case Intrinsic::riscv_vse: {
+ bool IsWrite = II->getType()->isVoidTy();
+ Type *Ty = IsWrite ? II->getArgOperand(0)->getType() : II->getType();
+ const auto *RVVIInfo = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo);
+ unsigned VLIndex = RVVIInfo->VLOperand;
+ unsigned PtrOperandNo = VLIndex - 1 - HasMask;
+ MaybeAlign Alignment =
+ II->getArgOperand(PtrOperandNo)->getPointerAlignment(DL);
+ Type *MaskType = Ty->getWithNewType(Type::getInt1Ty(C));
+ Value *Mask = ConstantInt::get(MaskType, 1);
+ if (HasMask)
+ Mask = II->getArgOperand(VLIndex - 1);
+ Value *EVL = II->getArgOperand(VLIndex);
+ Interesting.emplace_back(II, PtrOperandNo, IsWrite, Ty, Alignment, Mask,
+ EVL);
+ return true;
+ }
+ case Intrinsic::riscv_vlse_mask:
+ case Intrinsic::riscv_vsse_mask:
+ HasMask = true;
+ [[fallthrough]];
+ case Intrinsic::riscv_vlse:
+ case Intrinsic::riscv_vsse: {
+ bool IsWrite = II->getType()->isVoidTy();
+ Type *Ty = IsWrite ? II->getArgOperand(0)->getType() : II->getType();
+ const auto *RVVIInfo = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntNo);
+ unsigned VLIndex = RVVIInfo->VLOperand;
+ unsigned PtrOperandNo = VLIndex - 2 - HasMask;
+ MaybeAlign Alignment =
+ II->getArgOperand(PtrOperandNo)->getPointerAlignment(DL);
+
+ Value *Stride = II->getArgOperand(PtrOperandNo + 1);
+ // Use the pointer alignment as the element alignment if the stride is a
+ // multiple of the pointer alignment. Otherwise, the element alignment
+ // should be Align(1).
+ unsigned PointerAlign = Alignment.valueOrOne().value();
+ if (!isa<ConstantInt>(Stride) ||
+ cast<ConstantInt>(Stride)->getZExtValue() % PointerAlign != 0)
+ Alignment = Align(1);
+
+ Type *MaskType = Ty->getWithNewType(Type::getInt1Ty(C));
+ Value *Mask = ConstantInt::get(MaskType, 1);
+ if (HasMask)
+ Mask = II->getArgOperand(VLIndex - 1);
+ Value *EVL = II->getArgOperand(VLIndex);
+ Interesting.emplace_back(II, PtrOperandNo, IsWrite, Ty, Alignment, Mask,
+ EVL, Stride);
+ return true;
+ }
+ case Intrinsic::riscv_masked_strided_load:
+ case Intrinsic::riscv_masked_strided_store: {
+ bool IsWrite = IntNo == Intrinsic::riscv_masked_strided_store;
+ Type *Ty = II->getArgOperand(0)->getType();
+ Value *Stride = II->getOperand(2);
+ // Use the pointer alignment as the element alignment if the stride is a
+ // mutiple of the pointer alignment. Otherwise, the element alignment
+ // should be Align(1).
+ MaybeAlign Alignment = II->getArgOperand(1)->getPointerAlignment(DL);
+ unsigned PointerAlign = Alignment.valueOrOne().value();
+ if (!isa<ConstantInt>(Stride) ||
+ cast<ConstantInt>(Stride)->getZExtValue() % PointerAlign != 0)
+ Alignment = Align(1);
+ Value *Mask = II->getArgOperand(3);
+ Interesting.emplace_back(II, /* PtrOperandNo */ 1, IsWrite, Ty, Alignment,
+ Mask, /* MaybeEVL */ nullptr, Stride);
+ return true;
+ }
+ }
+ return false;
+}
+
InstructionCost
RISCVTTIImpl::getRISCVInstructionCost(ArrayRef<unsigned> OpCodes, MVT VT,
TTI::TargetCostKind CostKind) {
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index c4d10aada1f4c..09851127a1e5a 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -60,6 +60,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
TLI(ST->getTargetLowering()) {}
+ bool getMemoryRefInfo(SmallVectorImpl<MemoryRefInfo> &Interesting,
+ IntrinsicInst *II) const;
+
bool areInlineCompatible(const Function *Caller,
const Function *Callee) const;
diff --git a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
index adf77f20cb1c7..8b30a1c191cda 100644
--- a/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
@@ -29,6 +29,7 @@
#include "llvm/Analysis/MemoryBuiltins.h"
#include "llvm/Analysis/StackSafetyAnalysis.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/BinaryFormat/MachO.h"
#include "llvm/Demangle/Demangle.h"
@@ -754,12 +755,13 @@ struct AddressSanitizer {
bool isInterestingAlloca(const AllocaInst &AI);
bool ignoreAccess(Instruction *Inst, Value *Ptr);
- void getInterestingMemoryOperands(
- Instruction *I, SmallVectorImpl<InterestingMemoryOperand> &Interesting);
+ void getMemoryRefInfos(Instruction *I,
+ SmallVectorImpl<MemoryRefInfo> &Interesting,
+ const TargetTransformInfo *TTI);
- void instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis,
- InterestingMemoryOperand &O, bool UseCalls,
- const DataLayout &DL, RuntimeCallInserter &RTCI);
+ void instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis, MemoryRefInfo &O,
+ bool UseCalls, const DataLayout &DL,
+ RuntimeCallInserter &RTCI);
void instrumentPointerComparisonOrSubtraction(Instruction *I,
RuntimeCallInserter &RTCI);
void instrumentAddress(Instruction *OrigIns, Instruction *InsertBefore,
@@ -795,7 +797,8 @@ struct AddressSanitizer {
void instrumentMemIntrinsic(MemIntrinsic *MI, RuntimeCallInserter &RTCI);
Value *memToShadow(Value *Shadow, IRBuilder<> &IRB);
bool suppressInstrumentationSiteForDebug(int &Instrumented);
- bool instrumentFunction(Function &F, const TargetLibraryInfo *TLI);
+ bool instrumentFunction(Function &F, const TargetLibraryInfo *TLI,
+ const TargetTransformInfo *TTI);
bool maybeInsertAsanInitAtFunctionEntry(Function &F);
bool maybeInsertDynamicShadowAtFunctionEntry(Function &F);
void markEscapedLocalAllocas(Function &F);
@@ -1264,7 +1267,8 @@ PreservedAnalyses AddressSanitizerPass::run(Module &M,
Options.MaxInlinePoisoningSize, Options.CompileKernel, Options.Recover,
Options.UseAfterScope, Options.UseAfterReturn);
const TargetLibraryInfo &TLI = FAM.getResult<TargetLibraryAnalysis>(F);
- Modified |= FunctionSanitizer.instrumentFunction(F, &TLI);
+ const TargetTransformInfo &TTI = FAM.getResult<TargetIRAnalysis>(F);
+ Modified |= FunctionSanitizer.instrumentFunction(F, &TLI, &TTI);
}
Modified |= ModuleSanitizer.instrumentModule(M);
if (!Modified)
@@ -1401,8 +1405,9 @@ bool AddressSanitizer::ignoreAccess(Instruction *Inst, Value *Ptr) {
return false;
}
-void AddressSanitizer::getInterestingMemoryOperands(
- Instruction *I, SmallVectorImpl<InterestingMemoryOperand> &Interesting) {
+void AddressSanitizer::getMemoryRefInfos(
+ Instruction *I, SmallVectorImpl<MemoryRefInfo> &Interesting,
+ const TargetTransformInfo *TTI) {
// Do not instrument the load fetching the dynamic shadow address.
if (LocalDynamicShadow == I)
return;
@@ -1520,6 +1525,9 @@ void AddressSanitizer::getInterestingMemoryOperands(
break;
}
default:
+ if (auto *II = dyn_cast<IntrinsicInst>(I))
+ if (TTI->getMemoryRefInfo(Interesting, II))
+ return;
for (unsigned ArgNo = 0; ArgNo < CI->arg_size(); ArgNo++) {
if (!ClInstrumentByval || !CI->isByValArgument(ArgNo) ||
ignoreAccess(I, CI->getArgOperand(ArgNo)))
@@ -1682,7 +1690,7 @@ void AddressSanitizer::instrumentMaskedLoadOrStore(
}
void AddressSanitizer::instrumentMop(ObjectSizeOffsetVisitor &ObjSizeVis,
- InterestingMemoryOperand &O, bool UseCalls,
+ MemoryRefInfo &O, bool UseCalls,
const DataLayout &DL,
RuntimeCallInserter &RTCI) {
Value *Addr = O.getPtr();
@@ -2941,7 +2949,8 @@ bool AddressSanitizer::suppressInstrumentationSiteForDebug(int &Instrumented) {
}
bool AddressSanitizer::instrumentFunction(Function &F,
- const TargetLibraryInfo *TLI) {
+ const TargetLibraryInfo *TLI,
+ const TargetTransformInfo *TTI) {
if (F.empty())
return false;
if (F.getLinkage() == GlobalValue::AvailableExternallyLinkage) return false;
@@ -2979,7 +2988,7 @@ bool AddressSanitizer::instrumentFunction(Function &F,
// We want to instrument every address only once per basic block (unless there
// are calls between uses).
SmallPtrSet<Value *, 16> TempsToInstrument;
- SmallVector<InterestingMemoryOperand, 16> OperandsToInstrument;
+ SmallVector<MemoryRefInfo, 16> OperandsToInstrument;
SmallVector<MemIntrinsic *, 16> IntrinToInstrument;
SmallVector<Instruction *, 8> NoReturnCalls;
SmallVector<BasicBlock *, 16> AllBlocks;
@@ -2995,8 +3004,8 @@ bool AddressSanitizer::instrumentFunction(Function &F,
// Skip instructions inserted by another instrumentation.
if (Inst.hasMetadata(LLVMContext::MD_nosanitize))
continue;
- SmallVector<InterestingMemoryOperand, 1> InterestingOperands;
- getInterestingMemoryOperands(&Inst, InterestingOperands);
+ SmallVector<MemoryRefInfo, 1> InterestingOperands;
+ getMemoryRefInfos(&Inst, InterestingOperands, TTI);
if (!InterestingOperands.empty()) {
for (auto &Operand : InterestingOperands) {
diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
index a0e63bf12400e..47212b2679e81 100644
--- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
@@ -339,16 +339,14 @@ class HWAddressSanitizer {
LoopInfo *LI);
bool ignoreMemIntrinsic(OptimizationRemarkEmitter &ORE, MemIntrinsic *MI);
void instrumentMemIntrinsic(MemIntrinsic *MI);
- bool instrumentMemAccess(InterestingMemoryOperand &O, DomTreeUpdater &DTU,
- LoopInfo *LI);
+ bool instrumentMemAccess(MemoryRefInfo &O, DomTreeUpdater &DTU, LoopInfo *LI);
bool ignoreAccessWithoutRemark(Instruction *Inst, Value *Ptr);
bool ignoreAccess(OptimizationRemarkEmitter &ORE, Instruction *Inst,
Value *Ptr);
- void getInterestingMemoryOperands(
- OptimizationRemarkEmitter &ORE, Instruction *I,
- const TargetLibraryInfo &TLI,
- SmallVectorImpl<InterestingMemoryOperand> &Interesting);
+ void getMemoryRefInfos(OptimizationRemarkEmitter &ORE, Instruction *I,
+ const TargetLibraryInfo &TLI,
+ SmallVectorImpl<MemoryRefInfo> &Interesting);
void tagAlloca(IRBuilder<> &IRB, AllocaInst *AI, Value *Tag, size_t Size);
Value *tagPointer(IRBuilder<> &IRB, Type *Ty, Value *PtrLong, Value *Tag);
@@ -814,10 +812,9 @@ bool HWAddressSanitizer::ignoreAccess(OptimizationRemarkEmitter &ORE,
return Ignored;
}
-void HWAddressSanitizer::getInterestingMemoryOperands(
+void HWAddressSanitizer::getMemoryRefInfos(
OptimizationRemarkEmitter &ORE, Instruction *I,
- const TargetLibraryInfo &TLI,
- SmallVectorImpl<InterestingMemoryOperand> &Interesting) {
+ const TargetLibraryInfo &TLI, SmallVectorImpl<MemoryRefInfo> &Interesting) {
// Skip memory acce...
[truncated]
|
|
Rebase and ping. |
topperc
reviewed
Jul 23, 2024
llvm/test/Instrumentation/AddressSanitizer/asan-rvv-intrinsics.ll
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…rget intrinsics. Previously asan considers target intrinsics as black boxes, so asan could not instrument accurate check. This patch provide TTI hooks to make targets describe their intrinsic informations to asan. Note, 1. this patch renames InterestingMemoryOperand to MemoryRefInfo. 2. this patch does not support RVV indexed/segment load/store.
yetingk
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…structions. This is based on llvm#97070. This patch helps AddressSanitizer to support indexed/segement instructions. It adds a new member maybeOffset inot MemoryRefInfo to describle the offset between the pointer and the address of this memory reference.
topperc
reviewed
Jul 31, 2024
topperc
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Jul 31, 2024
topperc
reviewed
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yetingk
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…structions. This is based on llvm#97070. This patch helps AddressSanitizer to support indexed/segement instructions. It adds a new member maybeOffset inot MemoryRefInfo to describle the offset between the pointer and the address of this memory reference.
topperc
reviewed
Aug 6, 2024
| Value *Stride = II->getArgOperand(PtrOperandNo + 1); | ||
| // Use the pointer alignment as the element alignment if the stride is a | ||
| // multiple of the pointer alignment. Otherwise, the element alignment | ||
| // should be the greatest of common divisor of pointer alignment and stride. |
There was a problem hiding this comment.
"greatest of common" -> "greatest common"
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…structions. This is based on llvm#97070. This patch helps AddressSanitizer to support indexed/segement instructions. It adds a new member maybeOffset inot MemoryRefInfo to describle the offset between the pointer and the address of this memory reference.
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/llvm-project/llvm/lib/Target/AMDGPU/AMDGPUAsanInstrumentation.h:55:21:
error: use of undeclared identifier 'InterestingMemoryOperand'
SmallVectorImpl<InterestingMemoryOperand> &Interesting);
^
yetingk
pushed a commit
to yetingk/llvm-project
that referenced
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Aug 8, 2024
…structions. This is based on llvm#97070. This patch helps AddressSanitizer to support indexed/segement instructions. It adds a new member maybeOffset inot MemoryRefInfo to describle the offset between the pointer and the address of this memory reference.
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@yetingk Hello and good morning from the UK. it looks like the test added in this commit has caused the following buildbots to start failing: https://lab.llvm.org/buildbot/#/builders/46/builds/2895 and no doubt many others. Are you able to take a look and get this fixed up? The bots have been red for a good few hours already. |
jmorse
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Aug 8, 2024
…on of target intrinsics. (#97070)" This reverts commit e8ad87c. This reverts commit d3c9bb0. A few buildbots trip up on asan-rvv-intrinsics.ll. I've also reverted the follow-up commit d3c9bb0. https://lab.llvm.org/buildbot/#/builders/46/builds/2895
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Reverted in bde2432 to clear the buildbots, plus a follow-up commit |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/56/builds/4356 Here is the relevant piece of the build log for the reference: |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/16/builds/3100 Here is the relevant piece of the build log for the reference: |
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LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/60/builds/4457 Here is the relevant piece of the build log for the reference: |
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Previously asan considers target intrinsics as black boxes, so asan could not instrument accurate check. This patch provide TTI hooks to make targets describe their intrinsic informations to asan.
Note,