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[X86] Enable alias analysis (AA) during codegen #123787

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[X86] Enable alias analysis (AA) during codegen #123787

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4 changes: 4 additions & 0 deletions llvm/lib/Target/X86/X86Subtarget.cpp
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Expand Up @@ -54,6 +54,8 @@ static cl::opt<bool>
X86EarlyIfConv("x86-early-ifcvt", cl::Hidden,
cl::desc("Enable early if-conversion on X86"));

static cl::opt<bool> UseAA("x86-use-aa", cl::init(true),
cl::desc("Enable the use of AA during codegen."));

/// Classify a blockaddress reference for the current subtarget according to how
/// we should reference it in a non-pcrel context.
Expand Down Expand Up @@ -320,6 +322,8 @@ void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
PreferVectorWidth = 256;
}

bool X86Subtarget::useAA() const { return UseAA; }

X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,
StringRef TuneCPU,
StringRef FS) {
Expand Down
2 changes: 2 additions & 0 deletions llvm/lib/Target/X86/X86Subtarget.h
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Expand Up @@ -155,6 +155,8 @@ class X86Subtarget final : public X86GenSubtargetInfo {
const LegalizerInfo *getLegalizerInfo() const override;
const RegisterBankInfo *getRegBankInfo() const override;

bool useAA() const override;

private:
/// Initialize the full set of dependencies so we can use an initializer
/// list for X86Subtarget.
Expand Down
35 changes: 13 additions & 22 deletions llvm/test/CodeGen/X86/2007-10-12-SpillerUnfold1.ll
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Expand Up @@ -4,32 +4,23 @@
define fastcc void @fht(ptr %fz, i16 signext %n) {
; CHECK-LABEL: fht:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
; CHECK-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
; CHECK-NEXT: xorps %xmm0, %xmm0
; CHECK-NEXT: xorps %xmm1, %xmm1
; CHECK-NEXT: subss %xmm3, %xmm1
; CHECK-NEXT: movaps %xmm3, %xmm4
; CHECK-NEXT: mulss %xmm0, %xmm4
; CHECK-NEXT: addss %xmm3, %xmm4
; CHECK-NEXT: movaps %xmm3, %xmm2
; CHECK-NEXT: subss %xmm4, %xmm2
; CHECK-NEXT: addss %xmm3, %xmm4
; CHECK-NEXT: xorps %xmm5, %xmm5
; CHECK-NEXT: subss %xmm1, %xmm5
; CHECK-NEXT: subss %xmm2, %xmm1
; CHECK-NEXT: movaps %xmm2, %xmm3
; CHECK-NEXT: mulss %xmm0, %xmm3
; CHECK-NEXT: addss %xmm2, %xmm3
; CHECK-NEXT: movaps %xmm2, %xmm4
; CHECK-NEXT: subss %xmm3, %xmm4
; CHECK-NEXT: addss %xmm0, %xmm1
; CHECK-NEXT: mulss %xmm0, %xmm4
; CHECK-NEXT: mulss %xmm0, %xmm5
; CHECK-NEXT: addss %xmm4, %xmm5
; CHECK-NEXT: addss %xmm0, %xmm5
; CHECK-NEXT: movss %xmm5, 0
; CHECK-NEXT: movss %xmm3, (%ecx)
; CHECK-NEXT: addss %xmm0, %xmm3
; CHECK-NEXT: movss %xmm3, 0
; CHECK-NEXT: mulss %xmm0, %xmm1
; CHECK-NEXT: mulss %xmm0, %xmm2
; CHECK-NEXT: addss %xmm1, %xmm2
; CHECK-NEXT: addss %xmm0, %xmm2
; CHECK-NEXT: movss %xmm2, (%ecx)
; CHECK-NEXT: movss %xmm2, 0
; CHECK-NEXT: mulss %xmm0, %xmm1
; CHECK-NEXT: mulss %xmm0, %xmm4
; CHECK-NEXT: addss %xmm1, %xmm4
; CHECK-NEXT: addss %xmm0, %xmm4
; CHECK-NEXT: movss %xmm4, (%ecx)
; CHECK-NEXT: retl
entry:
br i1 true, label %bb171.preheader, label %bb431
Expand Down
1 change: 0 additions & 1 deletion llvm/test/CodeGen/X86/2008-03-31-SpillerFoldingBug.ll
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Expand Up @@ -34,7 +34,6 @@ define void @_GLOBAL__I__ZN5Pooma5pinfoE() nounwind {
; CHECK-NEXT: movl %eax, %esi
; CHECK-NEXT: movl $0, (%esp)
; CHECK-NEXT: calll __ZNSt8ios_baseC2Ev
; CHECK-NEXT: movl $0, 0
; CHECK-NEXT: addl $12, %ebx
; CHECK-NEXT: movl %ebx, (%esi)
; CHECK-NEXT: movl L__ZTVSt15basic_streambufIcSt11char_traitsIcEE$non_lazy_ptr-L0$pb(%edi), %eax
Expand Down
84 changes: 38 additions & 46 deletions llvm/test/CodeGen/X86/MergeConsecutiveStores.ll
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Expand Up @@ -402,9 +402,9 @@ define void @merge_loads_i16(i32 %count, ptr noalias nocapture %q, ptr noalias n
define void @no_merge_loads(i32 %count, ptr noalias nocapture %q, ptr noalias nocapture %p) nounwind uwtable noinline ssp {
; X86-BWON-LABEL: no_merge_loads:
; X86-BWON: # %bb.0:
; X86-BWON-NEXT: pushl %ebx
; X86-BWON-NEXT: pushl %esi
; X86-BWON-NEXT: .cfi_def_cfa_offset 8
; X86-BWON-NEXT: .cfi_offset %ebx, -8
; X86-BWON-NEXT: .cfi_offset %esi, -8
; X86-BWON-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BWON-NEXT: testl %eax, %eax
; X86-BWON-NEXT: jle .LBB5_3
Expand All @@ -414,23 +414,21 @@ define void @no_merge_loads(i32 %count, ptr noalias nocapture %q, ptr noalias no
; X86-BWON-NEXT: .p2align 4
; X86-BWON-NEXT: .LBB5_2: # %a4
; X86-BWON-NEXT: # =>This Inner Loop Header: Depth=1
; X86-BWON-NEXT: movzbl (%edx), %ebx
; X86-BWON-NEXT: movb %bl, (%ecx)
; X86-BWON-NEXT: movzbl 1(%edx), %ebx
; X86-BWON-NEXT: movb %bl, 1(%ecx)
; X86-BWON-NEXT: movzwl (%edx), %esi
; X86-BWON-NEXT: movw %si, (%ecx)
; X86-BWON-NEXT: addl $8, %ecx
; X86-BWON-NEXT: decl %eax
; X86-BWON-NEXT: jne .LBB5_2
; X86-BWON-NEXT: .LBB5_3: # %._crit_edge
; X86-BWON-NEXT: popl %ebx
; X86-BWON-NEXT: popl %esi
; X86-BWON-NEXT: .cfi_def_cfa_offset 4
; X86-BWON-NEXT: retl
;
; X86-BWOFF-LABEL: no_merge_loads:
; X86-BWOFF: # %bb.0:
; X86-BWOFF-NEXT: pushl %ebx
; X86-BWOFF-NEXT: pushl %esi
; X86-BWOFF-NEXT: .cfi_def_cfa_offset 8
; X86-BWOFF-NEXT: .cfi_offset %ebx, -8
; X86-BWOFF-NEXT: .cfi_offset %esi, -8
; X86-BWOFF-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BWOFF-NEXT: testl %eax, %eax
; X86-BWOFF-NEXT: jle .LBB5_3
Expand All @@ -440,15 +438,13 @@ define void @no_merge_loads(i32 %count, ptr noalias nocapture %q, ptr noalias no
; X86-BWOFF-NEXT: .p2align 4
; X86-BWOFF-NEXT: .LBB5_2: # %a4
; X86-BWOFF-NEXT: # =>This Inner Loop Header: Depth=1
; X86-BWOFF-NEXT: movb (%edx), %bl
; X86-BWOFF-NEXT: movb %bl, (%ecx)
; X86-BWOFF-NEXT: movb 1(%edx), %bl
; X86-BWOFF-NEXT: movb %bl, 1(%ecx)
; X86-BWOFF-NEXT: movw (%edx), %si
; X86-BWOFF-NEXT: movw %si, (%ecx)
; X86-BWOFF-NEXT: addl $8, %ecx
; X86-BWOFF-NEXT: decl %eax
; X86-BWOFF-NEXT: jne .LBB5_2
; X86-BWOFF-NEXT: .LBB5_3: # %._crit_edge
; X86-BWOFF-NEXT: popl %ebx
; X86-BWOFF-NEXT: popl %esi
; X86-BWOFF-NEXT: .cfi_def_cfa_offset 4
; X86-BWOFF-NEXT: retl
;
Expand All @@ -459,10 +455,8 @@ define void @no_merge_loads(i32 %count, ptr noalias nocapture %q, ptr noalias no
; X64-BWON-NEXT: .p2align 4
; X64-BWON-NEXT: .LBB5_1: # %a4
; X64-BWON-NEXT: # =>This Inner Loop Header: Depth=1
; X64-BWON-NEXT: movzbl (%rsi), %eax
; X64-BWON-NEXT: movb %al, (%rdx)
; X64-BWON-NEXT: movzbl 1(%rsi), %eax
; X64-BWON-NEXT: movb %al, 1(%rdx)
; X64-BWON-NEXT: movzwl (%rsi), %eax
; X64-BWON-NEXT: movw %ax, (%rdx)
; X64-BWON-NEXT: addq $8, %rdx
; X64-BWON-NEXT: decl %edi
; X64-BWON-NEXT: jne .LBB5_1
Expand All @@ -476,10 +470,8 @@ define void @no_merge_loads(i32 %count, ptr noalias nocapture %q, ptr noalias no
; X64-BWOFF-NEXT: .p2align 4
; X64-BWOFF-NEXT: .LBB5_1: # %a4
; X64-BWOFF-NEXT: # =>This Inner Loop Header: Depth=1
; X64-BWOFF-NEXT: movb (%rsi), %al
; X64-BWOFF-NEXT: movb %al, (%rdx)
; X64-BWOFF-NEXT: movb 1(%rsi), %al
; X64-BWOFF-NEXT: movb %al, 1(%rdx)
; X64-BWOFF-NEXT: movw (%rsi), %ax
; X64-BWOFF-NEXT: movw %ax, (%rdx)
; X64-BWOFF-NEXT: addq $8, %rdx
; X64-BWOFF-NEXT: decl %edi
; X64-BWOFF-NEXT: jne .LBB5_1
Expand Down Expand Up @@ -858,26 +850,26 @@ define void @MergeLoadStoreBaseIndexOffsetComplicated(ptr %a, ptr %b, ptr %c, i6
; X86-BWON-NEXT: .cfi_offset %edi, -16
; X86-BWON-NEXT: .cfi_offset %ebx, -12
; X86-BWON-NEXT: .cfi_offset %ebp, -8
; X86-BWON-NEXT: xorl %eax, %eax
; X86-BWON-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BWON-NEXT: xorl %esi, %esi
; X86-BWON-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BWON-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-BWON-NEXT: xorl %ebp, %ebp
; X86-BWON-NEXT: .p2align 4
; X86-BWON-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; X86-BWON-NEXT: movsbl (%edi), %ecx
; X86-BWON-NEXT: movzbl (%esi,%ecx), %edx
; X86-BWON-NEXT: movzbl 1(%esi,%ecx), %ecx
; X86-BWON-NEXT: movb %dl, (%ebx,%eax)
; X86-BWON-NEXT: movl %eax, %edx
; X86-BWON-NEXT: orl $1, %edx
; X86-BWON-NEXT: movb %cl, (%ebx,%edx)
; X86-BWON-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BWON-NEXT: movzbl (%eax,%ecx), %edx
; X86-BWON-NEXT: movzbl 1(%eax,%ecx), %ecx
; X86-BWON-NEXT: movl %esi, %eax
; X86-BWON-NEXT: orl $1, %eax
; X86-BWON-NEXT: movb %cl, (%ebx,%eax)
; X86-BWON-NEXT: movb %dl, (%ebx,%esi)
; X86-BWON-NEXT: incl %edi
; X86-BWON-NEXT: addl $2, %eax
; X86-BWON-NEXT: addl $2, %esi
; X86-BWON-NEXT: adcl $0, %ebp
; X86-BWON-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; X86-BWON-NEXT: movl %ebp, %ecx
; X86-BWON-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
; X86-BWON-NEXT: cmpl {{[0-9]+}}(%esp), %esi
; X86-BWON-NEXT: movl %ebp, %eax
; X86-BWON-NEXT: sbbl {{[0-9]+}}(%esp), %eax
; X86-BWON-NEXT: jl .LBB10_1
; X86-BWON-NEXT: # %bb.2:
; X86-BWON-NEXT: popl %esi
Expand All @@ -904,26 +896,26 @@ define void @MergeLoadStoreBaseIndexOffsetComplicated(ptr %a, ptr %b, ptr %c, i6
; X86-BWOFF-NEXT: .cfi_offset %edi, -16
; X86-BWOFF-NEXT: .cfi_offset %ebx, -12
; X86-BWOFF-NEXT: .cfi_offset %ebp, -8
; X86-BWOFF-NEXT: xorl %eax, %eax
; X86-BWOFF-NEXT: movl {{[0-9]+}}(%esp), %esi
; X86-BWOFF-NEXT: xorl %esi, %esi
; X86-BWOFF-NEXT: movl {{[0-9]+}}(%esp), %edi
; X86-BWOFF-NEXT: movl {{[0-9]+}}(%esp), %ebx
; X86-BWOFF-NEXT: xorl %ebp, %ebp
; X86-BWOFF-NEXT: .p2align 4
; X86-BWOFF-NEXT: .LBB10_1: # =>This Inner Loop Header: Depth=1
; X86-BWOFF-NEXT: movsbl (%edi), %ecx
; X86-BWOFF-NEXT: movb (%esi,%ecx), %dl
; X86-BWOFF-NEXT: movb 1(%esi,%ecx), %cl
; X86-BWOFF-NEXT: movb %dl, (%ebx,%eax)
; X86-BWOFF-NEXT: movl %eax, %edx
; X86-BWOFF-NEXT: orl $1, %edx
; X86-BWOFF-NEXT: movb %cl, (%ebx,%edx)
; X86-BWOFF-NEXT: movl {{[0-9]+}}(%esp), %eax
; X86-BWOFF-NEXT: movb (%eax,%ecx), %dl
; X86-BWOFF-NEXT: movb 1(%eax,%ecx), %cl
; X86-BWOFF-NEXT: movl %esi, %eax
; X86-BWOFF-NEXT: orl $1, %eax
; X86-BWOFF-NEXT: movb %cl, (%ebx,%eax)
; X86-BWOFF-NEXT: movb %dl, (%ebx,%esi)
; X86-BWOFF-NEXT: incl %edi
; X86-BWOFF-NEXT: addl $2, %eax
; X86-BWOFF-NEXT: addl $2, %esi
; X86-BWOFF-NEXT: adcl $0, %ebp
; X86-BWOFF-NEXT: cmpl {{[0-9]+}}(%esp), %eax
; X86-BWOFF-NEXT: movl %ebp, %ecx
; X86-BWOFF-NEXT: sbbl {{[0-9]+}}(%esp), %ecx
; X86-BWOFF-NEXT: cmpl {{[0-9]+}}(%esp), %esi
; X86-BWOFF-NEXT: movl %ebp, %eax
; X86-BWOFF-NEXT: sbbl {{[0-9]+}}(%esp), %eax
; X86-BWOFF-NEXT: jl .LBB10_1
; X86-BWOFF-NEXT: # %bb.2:
; X86-BWOFF-NEXT: popl %esi
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/addcarry.ll
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Expand Up @@ -1155,14 +1155,14 @@ define void @PR39464(ptr noalias nocapture sret(%struct.U192) %0, ptr nocapture
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: movq (%rsi), %rcx
; CHECK-NEXT: movq 8(%rsi), %rdi
; CHECK-NEXT: addq (%rdx), %rcx
; CHECK-NEXT: movq %rcx, (%rdi)
; CHECK-NEXT: movq 8(%rsi), %rcx
; CHECK-NEXT: adcq 8(%rdx), %rcx
; CHECK-NEXT: movq %rcx, 8(%rdi)
; CHECK-NEXT: movq %rcx, (%rax)
; CHECK-NEXT: adcq 8(%rdx), %rdi
; CHECK-NEXT: movq %rdi, 8(%rax)
; CHECK-NEXT: movq 16(%rsi), %rcx
; CHECK-NEXT: adcq 16(%rdx), %rcx
; CHECK-NEXT: movq %rcx, 16(%rdi)
; CHECK-NEXT: movq %rcx, 16(%rax)
; CHECK-NEXT: retq
%4 = load i64, ptr %1, align 8
%5 = load i64, ptr %2, align 8
Expand Down
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