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[win/asan] GetInstructionSize: Support some more 4 byte instructions. #123709

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merged 1 commit into from
Jan 22, 2025
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[win/asan] GetInstructionSize: Support some more 4 byte instructions. #123709

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11 changes: 11 additions & 0 deletions compiler-rt/lib/interception/interception_win.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -666,6 +666,9 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
}

switch (0x00FFFFFF & *(u32 *)address) {
case 0x244C8D: // 8D 4C 24 XX : lea ecx, [esp + XX]
case 0x2474FF: // FF 74 24 XX : push qword ptr [rsp + XX]
return 4;
case 0x24A48D: // 8D A4 24 XX XX XX XX : lea esp, [esp + XX XX XX XX]
return 7;
}
Expand Down Expand Up @@ -829,6 +832,10 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0x588948: // 48 89 58 XX : mov QWORD PTR[rax + XX], rbx
case 0xec8348: // 48 83 ec XX : sub rsp, XX
case 0xf88349: // 49 83 f8 XX : cmp r8, XX
case 0x488d49: // 49 8d 48 XX : lea rcx, [...]
case 0x048d4c: // 4c 8d 04 XX : lea r8, [...]
case 0x148d4e: // 4e 8d 14 XX : lea r10, [...]
case 0x398366: // 66 83 39 XX : cmp WORD PTR [rcx], XX
return 4;

case 0x246483: // 83 64 24 XX YY : and DWORD PTR [rsp+XX], YY
Expand Down Expand Up @@ -883,6 +890,10 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
}

switch (*(u32*)(address)) {
case 0x01b60f44: // 44 0f b6 01 : movzx r8d, BYTE PTR [rcx]
case 0x09b60f44: // 44 0f b6 09 : movzx r9d, BYTE PTR [rcx]
case 0x0ab60f44: // 44 0f b6 0a : movzx r8d, BYTE PTR [rdx]
case 0x11b60f44: // 44 0f b6 11 : movzx r10d, BYTE PTR [rcx]
case 0x1ab60f44: // 44 0f b6 1a : movzx r11d, BYTE PTR [rdx]
return 4;
case 0x24448b48: // 48 8b 44 24 XX : mov rax, QWORD ptr [rsp + XX]
Expand Down
10 changes: 10 additions & 0 deletions compiler-rt/lib/interception/tests/interception_win_test.cpp
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Expand Up @@ -864,6 +864,8 @@ const struct InstructionSizeData {
{ 3, {0x8B, 0x55, 0x72}, 0, "8B 55 XX : mov XX(%ebp), edx"},
{ 3, {0x8B, 0x75, 0x72}, 0, "8B 75 XX : mov XX(%ebp), esp"},
{ 3, {0xc2, 0x71, 0x72}, 0, "C2 XX XX : ret XX (needed for registering weak functions)"},
{ 4, {0x8D, 0x4C, 0x24, 0x73}, 0, "8D 4C 24 XX : lea ecx, [esp + XX]"},
{ 4, {0xFF, 0x74, 0x24, 0x73}, 0, "FF 74 24 XX : push qword ptr [rsp + XX]"},
{ 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"},
{ 5, {0xb8, 0x71, 0x72, 0x73, 0x74}, 0, "b8 XX XX XX XX : mov eax, XX XX XX XX"},
{ 5, {0xB9, 0x71, 0x72, 0x73, 0x74}, 0, "b9 XX XX XX XX : mov ecx, XX XX XX XX"},
Expand Down Expand Up @@ -961,11 +963,19 @@ const struct InstructionSizeData {
{ 3, {0x4d, 0x85, 0xf6}, 0, "4d 85 f6 : test r14, r14"},
{ 3, {0x4d, 0x85, 0xff}, 0, "4d 85 ff : test r15, r15"},
{ 3, {0xf6, 0xc1, 0x72}, 0, "f6 c1 XX : test cl, XX"},
{ 4, {0x44, 0x0f, 0xb6, 0x01}, 0, "44 0f b6 01 : movzx r8d, BYTE PTR [rcx]"},
{ 4, {0x44, 0x0f, 0xb6, 0x09}, 0, "44 0f b6 09 : movzx r9d, BYTE PTR [rcx]"},
{ 4, {0x44, 0x0f, 0xb6, 0x0a}, 0, "44 0f b6 0a : movzx r8d, BYTE PTR [rdx]"},
{ 4, {0x44, 0x0f, 0xb6, 0x11}, 0, "44 0f b6 11 : movzx r10d, BYTE PTR [rcx]"},
{ 4, {0x44, 0x0f, 0xb6, 0x1a}, 0, "44 0f b6 1a : movzx r11d, BYTE PTR [rdx]"},
{ 4, {0x44, 0x8d, 0x42, 0x73}, 0, "44 8d 42 XX : lea r8d , [rdx + XX]"},
{ 4, {0x48, 0x83, 0xec, 0x73}, 0, "48 83 ec XX : sub rsp, XX"},
{ 4, {0x48, 0x89, 0x58, 0x73}, 0, "48 89 58 XX : mov QWORD PTR[rax + XX], rbx"},
{ 4, {0x49, 0x83, 0xf8, 0x73}, 0, "49 83 f8 XX : cmp r8, XX"},
{ 4, {0x49, 0x8d, 0x48, 0x73}, 0, "49 8d 48 XX : lea rcx, [...]"},
{ 4, {0x4c, 0x8d, 0x04, 0x73}, 0, "4c 8d 04 XX : lea r8, [...]"},
{ 4, {0x4e, 0x8d, 0x14, 0x73}, 0, "4e 8d 14 XX : lea r10, [...]"},
{ 4, {0x66, 0x83, 0x39, 0x73}, 0, "66 83 39 XX : cmp WORD PTR [rcx], XX"},
{ 4, {0x80, 0x78, 0x72, 0x73}, 0, "80 78 YY XX : cmp BYTE PTR [rax+YY], XX"},
{ 4, {0x80, 0x79, 0x72, 0x73}, 0, "80 79 YY XX : cmp BYTE ptr [rcx+YY], XX"},
{ 4, {0x80, 0x7A, 0x72, 0x73}, 0, "80 7A YY XX : cmp BYTE PTR [rdx+YY], XX"},
Expand Down
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