[DAGCombiner] Fix scalarizeExtractedBinOp for some SETCC cases #123071
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@llvm/pr-subscribers-llvm-selectiondag Author: David Sherwood (david-arm) ChangesPR #118823 added a Fixes #121372 Full diff: https://github.com/llvm/llvm-project/pull/123071.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6805e0cb23ace0..817c1c21718236 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22809,7 +22809,8 @@ static SDValue scalarizeExtractedBinOp(SDNode *ExtElt, SelectionDAG &DAG,
EVT ResVT = ExtElt->getValueType(0);
if (Opc == ISD::SETCC &&
- (ResVT != Vec.getValueType().getVectorElementType() || LegalTypes))
+ (ResVT != Vec.getValueType().getVectorElementType() || ResVT != MVT::i1 ||
+ LegalTypes))
return SDValue();
// Targets may want to avoid this to prevent an expensive register transfer.
diff --git a/llvm/test/CodeGen/AArch64/extract-vector-cmp.ll b/llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
index 12bd2db2297d77..38961ae6227bfa 100644
--- a/llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
+++ b/llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
@@ -58,10 +58,11 @@ define i128 @extract_icmp_v1i128(ptr %p) {
; CHECK-LABEL: extract_icmp_v1i128:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp x9, x8, [x0]
-; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: orr x8, x9, x8
; CHECK-NEXT: cmp x8, #0
-; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: cset w8, eq
+; CHECK-NEXT: sbfx x0, x8, #0, #1
+; CHECK-NEXT: mov x1, x0
; CHECK-NEXT: ret
%load = load <1 x i128>, ptr %p, align 16
%cmp = icmp eq <1 x i128> %load, zeroinitializer
@@ -141,6 +142,24 @@ for.cond.cleanup:
}
+define i32 @issue_121372(<4 x i32> %0) {
+; CHECK-LABEL: issue_121372:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: cmp w8, #1
+; CHECK-NEXT: csetm w0, lt
+; CHECK-NEXT: ret
+ %2 = icmp ule <4 x i32> %0, zeroinitializer
+ %3 = sext <4 x i1> %2 to <4 x i32>
+ %4 = icmp sge <4 x i32> zeroinitializer, %3
+ %5 = extractelement <4 x i1> %4, i32 0
+ %6 = sext i1 %5 to i32
+ ret i32 %6
+}
+
+
; Negative tests
define i1 @extract_icmp_v4i32_splat_rhs(<4 x i32> %a, i32 %b) {
@@ -163,9 +182,9 @@ define i1 @extract_icmp_v4i32_splat_rhs_mul_use(<4 x i32> %a, ptr %p) {
; CHECK-LABEL: extract_icmp_v4i32_splat_rhs_mul_use:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #235
-; CHECK-NEXT: adrp x9, .LCPI7_0
+; CHECK-NEXT: adrp x9, .LCPI8_0
; CHECK-NEXT: mov x8, x0
-; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI7_0]
+; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI8_0]
; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT: xtn v1.4h, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
|
@llvm/pr-subscribers-backend-aarch64 Author: David Sherwood (david-arm) ChangesPR #118823 added a Fixes #121372 Full diff: https://github.com/llvm/llvm-project/pull/123071.diff 2 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6805e0cb23ace0..817c1c21718236 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -22809,7 +22809,8 @@ static SDValue scalarizeExtractedBinOp(SDNode *ExtElt, SelectionDAG &DAG,
EVT ResVT = ExtElt->getValueType(0);
if (Opc == ISD::SETCC &&
- (ResVT != Vec.getValueType().getVectorElementType() || LegalTypes))
+ (ResVT != Vec.getValueType().getVectorElementType() || ResVT != MVT::i1 ||
+ LegalTypes))
return SDValue();
// Targets may want to avoid this to prevent an expensive register transfer.
diff --git a/llvm/test/CodeGen/AArch64/extract-vector-cmp.ll b/llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
index 12bd2db2297d77..38961ae6227bfa 100644
--- a/llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
+++ b/llvm/test/CodeGen/AArch64/extract-vector-cmp.ll
@@ -58,10 +58,11 @@ define i128 @extract_icmp_v1i128(ptr %p) {
; CHECK-LABEL: extract_icmp_v1i128:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp x9, x8, [x0]
-; CHECK-NEXT: mov x1, xzr
; CHECK-NEXT: orr x8, x9, x8
; CHECK-NEXT: cmp x8, #0
-; CHECK-NEXT: cset w0, eq
+; CHECK-NEXT: cset w8, eq
+; CHECK-NEXT: sbfx x0, x8, #0, #1
+; CHECK-NEXT: mov x1, x0
; CHECK-NEXT: ret
%load = load <1 x i128>, ptr %p, align 16
%cmp = icmp eq <1 x i128> %load, zeroinitializer
@@ -141,6 +142,24 @@ for.cond.cleanup:
}
+define i32 @issue_121372(<4 x i32> %0) {
+; CHECK-LABEL: issue_121372:
+; CHECK: // %bb.0:
+; CHECK-NEXT: movi v1.2d, #0000000000000000
+; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
+; CHECK-NEXT: fmov w8, s0
+; CHECK-NEXT: cmp w8, #1
+; CHECK-NEXT: csetm w0, lt
+; CHECK-NEXT: ret
+ %2 = icmp ule <4 x i32> %0, zeroinitializer
+ %3 = sext <4 x i1> %2 to <4 x i32>
+ %4 = icmp sge <4 x i32> zeroinitializer, %3
+ %5 = extractelement <4 x i1> %4, i32 0
+ %6 = sext i1 %5 to i32
+ ret i32 %6
+}
+
+
; Negative tests
define i1 @extract_icmp_v4i32_splat_rhs(<4 x i32> %a, i32 %b) {
@@ -163,9 +182,9 @@ define i1 @extract_icmp_v4i32_splat_rhs_mul_use(<4 x i32> %a, ptr %p) {
; CHECK-LABEL: extract_icmp_v4i32_splat_rhs_mul_use:
; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.4s, #235
-; CHECK-NEXT: adrp x9, .LCPI7_0
+; CHECK-NEXT: adrp x9, .LCPI8_0
; CHECK-NEXT: mov x8, x0
-; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI7_0]
+; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI8_0]
; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s
; CHECK-NEXT: xtn v1.4h, v0.4s
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
arsenm
reviewed
Jan 16, 2025
| ; CHECK-NEXT: cmp w8, #1 | ||
| ; CHECK-NEXT: csetm w0, lt | ||
| ; CHECK-NEXT: ret | ||
| %2 = icmp ule <4 x i32> %0, zeroinitializer |
PR llvm#118823 added a DAG combine for extracting elements of a vector returned from SETCC, however it doesn't correctly deal with the case where the vector element type is not i1. In this case we have to take account of the boolean contents, which are represent differently between vectors and scalars. The code now explicitly performs an inreg sign extend in order to get the same result. Fixes llvm#121372
david-arm
changed the title
davemgreen
reviewed
Jan 17, 2025
davemgreen
approved these changes
Jan 20, 2025
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PR #118823 added a
DAG combine for extracting elements of a vector returned from
SETCC, however it doesn't correctly deal with the case where
the vector element type is not i1. In this case we have to
take account of the boolean contents, which are represented
differently between vectors and scalars. The code now
explicitly performs an inreg sign extend in order to get the
same result.
Fixes #121372