Fix calculation of SPI_MIN_CLOCK_DIVIDER in SPI.h #292
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The previous version of SPI.h works only for the SAMD21G18A variant and only for a 48 MHz system clock. For the rest of variants, it sets SPI_MIN_CLOCK_DIVIDER to 2, which is incorrect for a 48 MHz system clock. The SAMD21 datasheet specifies a typical SPI SCK period (tSCK) of 42 ns, see "Table 36-48. SPI Timing Characteristics and Requirements", which translates into a maximum SPI clock of 23.8 MHz. The new code conservatively sets the divider for a 12 MHz maximum SPI clock, taking into account any value for the system clock (not only 48 MHz). It also executes for other variants of the SAMD, not only SAMD21G18A. Can you, please, review this patch?
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Additional clarification:
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I remember that we did some tests with 24Mhz SPI clock, but turned out that the CLK front was off of some nanoseconds making it incompatible with Mode 3 devices. Moreover, at the times, an Atmel' engineer confirmed that the maximum clock speed for the SAMD21 is 12MHz. BTW if your experience is different, and 24MHz is possible, I'd like to hear more about that. |
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My experience is positive with SPI clocks between 12 and 24 MHz, with good PCB layout, short & narrow (5-6 mils) tracks. I have not tested, however, a SAMD21 device above 24 MHz. For that, you have to take into account the I/O pins electrical specifications and the external loading of the SPI pins, that's where PCB layout vs. breadboarding makes a huge difference. In short, the maximum reliable SPI clock heavily depends on the external loading. According to the datasheet (Table 36-13. Normal I/O Pins Characteristics), the rise/fall times of the output SPI pins can be up to 15 ns for an external pin load capacitance of 5/20 nF, depending on the value of PORT.PINCFG.DRVSTR (pin driver). For DRVSTR = 0, a maximum capacitance of 5 pF should be present at the output SPI pins. That explains the CLK front delay you observed. In short, to attain a reliable 24 MHz SPI communication, you will need less than 5 pF external capacitance (DRVSTR = 0) or 20 pF (DRVSTR = 1), which may be not feasible with breadboarding and/or long wires. It also depends on the load capacitance of the slave SPI chip pins. On the one hand, being conservative and sticking to a 12 MHz max clock will help enthusiasts to continue using breadboarding with Arduino Zero without too much trouble. On the other hand, it will limit other designers willing to attain higher clocks under a controlled PCB layout setup. |
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Thanks to @ladyada for pointing out that the latest datasheet (rev. A dated 01/2017) clearly indicates a typical tSCK = 84 ns, which roughly translates into a maximum SPI clock of 12 MHz. That pretty much settles the matter. P.S.: Atmel definitely changed this specification at some point. My old locally stored datasheet rev 42181D (dated 09/2014), indicates tSCK (typ.) = 42 ns (roughly 24 MHz). Wow! |
Oh good to know, better late than never :-) Thanks for sharing your experience anyway! |
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Changing the line 45 of the SPI Library SPI is 24Mhz. https://snipboard.io/7f5uxT.jpg The board is this: SAMD21 connected ar RAIO 8876M SPI TFT controller and SD reader. Signal is good, but devices do not work. |
The previous version of SPI.h works only for the SAMD21G18A variant and only for a 48 MHz system clock. For the rest of variants, it sets SPI_MIN_CLOCK_DIVIDER to 2, which is incorrect for a 48 MHz system clock.
The SAMD21 datasheet specifies a typical SPI SCK period (tSCK) of 42 ns, see "Table 36-48. SPI Timing Characteristics and Requirements", which translates into a maximum SPI clock of 23.8 MHz.
The new code conservatively sets the divider for a 12 MHz maximum SPI clock, taking into account any value for the system clock (not only 48 MHz). It also executes for other variants of the SAMD, not only SAMD21G18A.
Can you, please, review this patch?