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[SelDag] Add isIntOrFPConstant helper function.
This patch adds a new isIntOrFPConstant helper function to check if a SDValue is a integer of FP constant. This pattern is used in various places. There also are places that incorrectly just check for integer constants, e.g. D99384, so hopefully this helper will help people avoid that issue. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D99428
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-7
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llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1684,6 +1684,11 @@ bool isOneOrOneSplat(SDValue V, bool AllowUndefs = false);
16841684
/// Does not permit build vector implicit truncation.
16851685
bool isAllOnesOrAllOnesSplat(SDValue V, bool AllowUndefs = false);
16861686

1687+
/// Return true if \p V is either a integer or FP constant.
1688+
inline bool isIntOrFPConstant(SDValue V) {
1689+
return isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V);
1690+
}
1691+
16871692
class GlobalAddressSDNode : public SDNode {
16881693
friend class SelectionDAG;
16891694

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -12413,7 +12413,7 @@ SDValue DAGCombiner::visitBITCAST(SDNode *N) {
1241312413
VT.getVectorElementType());
1241412414

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// If the input is a constant, let getNode fold it.
12416-
if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
12416+
if (isIntOrFPConstant(N0)) {
1241712417
// If we can't allow illegal operations, we need to check that this is just
1241812418
// a fp -> int or int -> conversion and that the resulting operation will
1241912419
// be legal.
@@ -12651,7 +12651,7 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) {
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return N0;
1265212652

1265312653
// If the input is a constant, return it.
12654-
if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0))
12654+
if (isIntOrFPConstant(N0))
1265512655
return N0;
1265612656

1265712657
return SDValue();
@@ -16912,7 +16912,7 @@ void DAGCombiner::getStoreMergeCandidates(
1691216912
case StoreSource::Constant:
1691316913
if (NoTypeMatch)
1691416914
return false;
16915-
if (!(isa<ConstantSDNode>(OtherBC) || isa<ConstantFPSDNode>(OtherBC)))
16915+
if (!isIntOrFPConstant(OtherBC))
1691616916
return false;
1691716917
break;
1691816918
case StoreSource::Extract:
@@ -20492,7 +20492,7 @@ static SDValue combineShuffleOfScalars(ShuffleVectorSDNode *SVN,
2049220492
// generating a splat; semantically, this is fine, but it's likely to
2049320493
// generate low-quality code if the target can't reconstruct an appropriate
2049420494
// shuffle.
20495-
if (!Op.isUndef() && !isa<ConstantSDNode>(Op) && !isa<ConstantFPSDNode>(Op))
20495+
if (!Op.isUndef() && !isIntOrFPConstant(Op))
2049620496
if (!IsSplat && !DuplicateOps.insert(Op).second)
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return SDValue();
2049820498

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9680,10 +9680,10 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
96809680
}
96819681
if (i > 0)
96829682
isOnlyLowElement = false;
9683-
if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
9683+
if (!isIntOrFPConstant(V))
96849684
isConstant = false;
96859685

9686-
if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
9686+
if (isIntOrFPConstant(V)) {
96879687
++NumConstantLanes;
96889688
if (!ConstantValue.getNode())
96899689
ConstantValue = V;
@@ -9849,7 +9849,7 @@ SDValue AArch64TargetLowering::LowerBUILD_VECTOR(SDValue Op,
98499849
for (unsigned i = 0; i < NumElts; ++i) {
98509850
SDValue V = Op.getOperand(i);
98519851
SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
9852-
if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V))
9852+
if (!isIntOrFPConstant(V))
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// Note that type legalization likely mucked about with the VT of the
98549854
// source operand, so we may have to convert it here before inserting.
98559855
Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);

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