Merge pull request #152 from Sh3Rm4n/rcc-pll-fix

Remove divisor check for HSE PRE_DIV

Author: Sh3Rm4n

CHANGELOG.md

@@ -20,6 +20,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Introduced auto-generated GPIO mappings based on the STM32CubeMX database
   ([#129](https://github.com/stm32-rs/stm32f3xx-hal/pull/129))
 
+- Fixed [#151][] not being 
+  able to generate 72 MHz HCLK for stm32f303xc devices ([#152](https://github.com/stm32-rs/stm32f3xx-hal/pull/152))
+
+[#151]: https://github.com/stm32-rs/stm32f3xx-hal/issues/151
+
 ## [v0.5.0] - 2020-07-21
 
 ### Added

src/rcc.rs

@@ -369,11 +369,9 @@ impl CFGR {
             let mut divisor = pllsrcclk / common_divisor;
 
             // Check if the multiplier can be represented by PLL_MUL
-            // or if the divisor can be represented by PRE_DIV
-            if multiplier == 1 || divisor == 1 {
+            if multiplier == 1 {
                 // PLL_MUL minimal value is 2
                 multiplier *= 2;
-                // PRE_DIV minimal value is 2
                 divisor *= 2;
             }