From 14ab01456bb0aed1a1d88d431095573762a8f199 Mon Sep 17 00:00:00 2001
From: Lzu Tao <taolzu@gmail.com>
Date: Sun, 28 Feb 2021 12:47:11 +0700
Subject: [PATCH 1/4] Add static_assert_imm_s{5,11,12,13} macros

---
 crates/core_arch/src/mips/msa/macros.rs | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/crates/core_arch/src/mips/msa/macros.rs b/crates/core_arch/src/mips/msa/macros.rs
index 1033e52b74..c955cb817b 100644
--- a/crates/core_arch/src/mips/msa/macros.rs
+++ b/crates/core_arch/src/mips/msa/macros.rs
@@ -1,11 +1,35 @@
 //! Utility macros.
 
+macro_rules! static_assert_imm_s5 {
+    ($imm:ident) => {
+        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -16, 15>::VALID;
+    };
+}
+
 macro_rules! static_assert_imm_s10 {
     ($imm:ident) => {
         let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -512, 511>::VALID;
     };
 }
 
+macro_rules! static_assert_imm_s11 {
+    ($imm:ident) => {
+        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -1024, 1022>::VALID;
+    };
+}
+
+macro_rules! static_assert_imm_s12 {
+    ($imm:ident) => {
+        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -2048, 2044>::VALID;
+    };
+}
+
+macro_rules! static_assert_imm_s13 {
+    ($imm:ident) => {
+        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -4096, 4088>::VALID;
+    };
+}
+
 //immediate value: -4096:4088
 macro_rules! constify_imm_s13 {
     ($imm_s13:expr, $expand:ident) => {

From 4452488e43a13dc444d08d2ced3d237543d09d07 Mon Sep 17 00:00:00 2001
From: Lzu Tao <taolzu@gmail.com>
Date: Mon, 1 Mar 2021 12:26:02 +0700
Subject: [PATCH 2/4] mips: Convert *const(1) to const generics

---
 crates/core_arch/src/mips/msa.rs | 1383 ++++++++++--------------------
 1 file changed, 463 insertions(+), 920 deletions(-)

diff --git a/crates/core_arch/src/mips/msa.rs b/crates/core_arch/src/mips/msa.rs
index c58af4b95c..ef4de1d81a 100644
--- a/crates/core_arch/src/mips/msa.rs
+++ b/crates/core_arch/src/mips/msa.rs
@@ -1411,14 +1411,10 @@ pub unsafe fn __msa_addv_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(addvi.b, imm5 = 0b10111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_addvi_b(a: v16i8, imm5: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_addvi_b(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_addvi_b<const IMM5: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm5!(IMM5);
+    msa_addvi_b(a, IMM5)
 }
 
 /// Immediate Add
@@ -1430,14 +1426,10 @@ pub unsafe fn __msa_addvi_b(a: v16i8, imm5: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(addvi.h, imm5 = 0b10111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_addvi_h(a: v8i16, imm5: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_addvi_h(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_addvi_h<const IMM5: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm5!(IMM5);
+    msa_addvi_h(a, IMM5)
 }
 
 /// Immediate Add
@@ -1449,14 +1441,10 @@ pub unsafe fn __msa_addvi_h(a: v8i16, imm5: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(addvi.w, imm5 = 0b10111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_addvi_w(a: v4i32, imm5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_addvi_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_addvi_w<const IMM5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm5!(IMM5);
+    msa_addvi_w(a, IMM5)
 }
 
 /// Immediate Add
@@ -1468,14 +1456,10 @@ pub unsafe fn __msa_addvi_w(a: v4i32, imm5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(addvi.d, imm5 = 0b10111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_addvi_d(a: v2i64, imm5: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_addvi_d(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_addvi_d<const IMM5: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm5!(IMM5);
+    msa_addvi_d(a, IMM5)
 }
 
 /// Vector Logical And
@@ -1501,14 +1485,10 @@ pub unsafe fn __msa_and_v(a: v16u8, b: v16u8) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(andi.b, imm8 = 0b10010111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_andi_b(a: v16u8, imm8: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm8:expr) => {
-            msa_andi_b(a, $imm8)
-        };
-    }
-    constify_imm8!(imm8, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_andi_b<const IMM8: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm8!(IMM8);
+    msa_andi_b(a, IMM8)
 }
 
 /// Vector Absolute Values of Signed Subtract
@@ -1928,14 +1908,10 @@ pub unsafe fn __msa_bclr_d(a: v2u64, b: v2u64) -> v2u64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bclri.b, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bclri_b(a: v16u8, imm3: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_bclri_b(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bclri_b<const IMM3: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm3!(IMM3);
+    msa_bclri_b(a, IMM3)
 }
 
 /// Immediate Bit Clear
@@ -1947,14 +1923,10 @@ pub unsafe fn __msa_bclri_b(a: v16u8, imm3: i32) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bclri.h, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bclri_h(a: v8u16, imm4: i32) -> v8u16 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_bclri_h(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bclri_h<const IMM4: i32>(a: v8u16) -> v8u16 {
+    static_assert_imm4!(IMM4);
+    msa_bclri_h(a, IMM4)
 }
 
 /// Immediate Bit Clear
@@ -1966,14 +1938,10 @@ pub unsafe fn __msa_bclri_h(a: v8u16, imm4: i32) -> v8u16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bclri.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bclri_w(a: v4u32, imm5: i32) -> v4u32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_bclri_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bclri_w<const IMM5: i32>(a: v4u32) -> v4u32 {
+    static_assert_imm5!(IMM5);
+    msa_bclri_w(a, IMM5)
 }
 
 /// Immediate Bit Clear
@@ -1985,14 +1953,10 @@ pub unsafe fn __msa_bclri_w(a: v4u32, imm5: i32) -> v4u32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bclri.d, imm6 = 0b111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bclri_d(a: v2u64, imm6: i32) -> v2u64 {
-    macro_rules! call {
-        ($imm6:expr) => {
-            msa_bclri_d(a, $imm6)
-        };
-    }
-    constify_imm6!(imm6, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bclri_d<const IMM6: i32>(a: v2u64) -> v2u64 {
+    static_assert_imm6!(IMM6);
+    msa_bclri_d(a, IMM6)
 }
 
 /// Vector Bit Insert Left
@@ -2390,14 +2354,10 @@ pub unsafe fn __msa_bneg_d(a: v2u64, b: v2u64) -> v2u64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bnegi.b, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bnegi_b(a: v16u8, imm3: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_bnegi_b(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bnegi_b<const IMM3: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm3!(IMM3);
+    msa_bnegi_b(a, IMM3)
 }
 
 /// Immediate Bit Negate
@@ -2409,14 +2369,10 @@ pub unsafe fn __msa_bnegi_b(a: v16u8, imm3: i32) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bnegi.h, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bnegi_h(a: v8u16, imm4: i32) -> v8u16 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_bnegi_h(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bnegi_h<const IMM4: i32>(a: v8u16) -> v8u16 {
+    static_assert_imm4!(IMM4);
+    msa_bnegi_h(a, IMM4)
 }
 
 /// Immediate Bit Negate
@@ -2428,14 +2384,10 @@ pub unsafe fn __msa_bnegi_h(a: v8u16, imm4: i32) -> v8u16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bnegi.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bnegi_w(a: v4u32, imm5: i32) -> v4u32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_bnegi_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bnegi_w<const IMM5: i32>(a: v4u32) -> v4u32 {
+    static_assert_imm5!(IMM5);
+    msa_bnegi_w(a, IMM5)
 }
 
 /// Immediate Bit Negate
@@ -2447,14 +2399,10 @@ pub unsafe fn __msa_bnegi_w(a: v4u32, imm5: i32) -> v4u32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bnegi.d, imm6 = 0b111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bnegi_d(a: v2u64, imm6: i32) -> v2u64 {
-    macro_rules! call {
-        ($imm6:expr) => {
-            msa_bnegi_d(a, $imm6)
-        };
-    }
-    constify_imm6!(imm6, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bnegi_d<const IMM6: i32>(a: v2u64) -> v2u64 {
+    static_assert_imm6!(IMM6);
+    msa_bnegi_d(a, IMM6)
 }
 
 /// Immediate Branch If All Elements Are Not Zero
@@ -2611,14 +2559,10 @@ pub unsafe fn __msa_bset_d(a: v2u64, b: v2u64) -> v2u64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bseti.b, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bseti_b(a: v16u8, imm3: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_bseti_b(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bseti_b<const IMM3: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm3!(IMM3);
+    msa_bseti_b(a, IMM3)
 }
 
 /// Immediate Bit Set
@@ -2630,14 +2574,10 @@ pub unsafe fn __msa_bseti_b(a: v16u8, imm3: i32) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bseti.h, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bseti_h(a: v8u16, imm4: i32) -> v8u16 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_bseti_h(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bseti_h<const IMM4: i32>(a: v8u16) -> v8u16 {
+    static_assert_imm4!(IMM4);
+    msa_bseti_h(a, IMM4)
 }
 
 /// Immediate Bit Set
@@ -2649,14 +2589,10 @@ pub unsafe fn __msa_bseti_h(a: v8u16, imm4: i32) -> v8u16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bseti.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bseti_w(a: v4u32, imm5: i32) -> v4u32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_bseti_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bseti_w<const IMM5: i32>(a: v4u32) -> v4u32 {
+    static_assert_imm5!(IMM5);
+    msa_bseti_w(a, IMM5)
 }
 
 /// Immediate Bit Set
@@ -2668,14 +2604,10 @@ pub unsafe fn __msa_bseti_w(a: v4u32, imm5: i32) -> v4u32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(bseti.d, imm6 = 0b111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_bseti_d(a: v2u64, imm6: i32) -> v2u64 {
-    macro_rules! call {
-        ($imm6:expr) => {
-            msa_bseti_d(a, $imm6)
-        };
-    }
-    constify_imm6!(imm6, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_bseti_d<const IMM6: i32>(a: v2u64) -> v2u64 {
+    static_assert_imm6!(IMM6);
+    msa_bseti_d(a, IMM6)
 }
 
 /// Immediate Branch If At Least One Element Is Zero
@@ -2795,14 +2727,10 @@ pub unsafe fn __msa_ceq_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(ceqi.b, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_ceqi_b(a: v16i8, imm_s5: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_ceqi_b(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_ceqi_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_ceqi_b(a, IMM_S5)
 }
 
 /// Immediate Compare Equal
@@ -2814,14 +2742,10 @@ pub unsafe fn __msa_ceqi_b(a: v16i8, imm_s5: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(ceqi.h, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_ceqi_h(a: v8i16, imm_s5: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_ceqi_h(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_ceqi_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_ceqi_h(a, IMM_S5)
 }
 
 /// Immediate Compare Equal
@@ -2833,14 +2757,10 @@ pub unsafe fn __msa_ceqi_h(a: v8i16, imm_s5: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(ceqi.w, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_ceqi_w(a: v4i32, imm_s5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_ceqi_w(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_ceqi_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_ceqi_w(a, IMM_S5)
 }
 
 /// Immediate Compare Equal
@@ -2852,14 +2772,10 @@ pub unsafe fn __msa_ceqi_w(a: v4i32, imm_s5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(ceqi.d, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_ceqi_d(a: v2i64, imm_s5: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_ceqi_d(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_ceqi_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_ceqi_d(a, IMM_S5)
 }
 
 /// GPR Copy from MSA Control Register
@@ -2998,14 +2914,10 @@ pub unsafe fn __msa_cle_u_d(a: v2u64, b: v2u64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clei_s.b, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clei_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_clei_s_b(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clei_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_clei_s_b(a, IMM_S5)
 }
 
 /// Immediate Compare Signed Less Than or Equal
@@ -3018,14 +2930,10 @@ pub unsafe fn __msa_clei_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clei_s.h, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clei_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_clei_s_h(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clei_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_clei_s_h(a, IMM_S5)
 }
 
 /// Immediate Compare Signed Less Than or Equal
@@ -3038,14 +2946,10 @@ pub unsafe fn __msa_clei_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clei_s.w, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clei_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_clei_s_w(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clei_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_clei_s_w(a, IMM_S5)
 }
 
 /// Immediate Compare Signed Less Than or Equal
@@ -3058,14 +2962,10 @@ pub unsafe fn __msa_clei_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clei_s.d, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clei_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_clei_s_d(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clei_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_clei_s_d(a, IMM_S5)
 }
 
 /// Immediate Compare Unsigned Less Than or Equal
@@ -3078,14 +2978,10 @@ pub unsafe fn __msa_clei_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clei_u.b, imm5 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clei_u_b(a: v16u8, imm5: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_clei_u_b(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clei_u_b<const IMM5: i32>(a: v16u8) -> v16i8 {
+    static_assert_imm5!(IMM5);
+    msa_clei_u_b(a, IMM5)
 }
 
 /// Immediate Compare Unsigned Less Than or Equal
@@ -3098,14 +2994,10 @@ pub unsafe fn __msa_clei_u_b(a: v16u8, imm5: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clei_u.h, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clei_u_h(a: v8u16, imm5: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_clei_u_h(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clei_u_h<const IMM5: i32>(a: v8u16) -> v8i16 {
+    static_assert_imm5!(IMM5);
+    msa_clei_u_h(a, IMM5)
 }
 
 /// Immediate Compare Unsigned Less Than or Equal
@@ -3118,14 +3010,10 @@ pub unsafe fn __msa_clei_u_h(a: v8u16, imm5: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clei_u.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clei_u_w(a: v4u32, imm5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_clei_u_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clei_u_w<const IMM5: i32>(a: v4u32) -> v4i32 {
+    static_assert_imm5!(IMM5);
+    msa_clei_u_w(a, IMM5)
 }
 
 /// Immediate Compare Unsigned Less Than or Equal
@@ -3138,14 +3026,10 @@ pub unsafe fn __msa_clei_u_w(a: v4u32, imm5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clei_u.d, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clei_u_d(a: v2u64, imm5: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_clei_u_d(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clei_u_d<const IMM5: i32>(a: v2u64) -> v2i64 {
+    static_assert_imm5!(IMM5);
+    msa_clei_u_d(a, IMM5)
 }
 
 /// Vector Compare Signed Less Than
@@ -3270,14 +3154,10 @@ pub unsafe fn __msa_clt_u_d(a: v2u64, b: v2u64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clti_s.b, imm_s5 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clti_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_clti_s_b(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clti_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_clti_s_b(a, IMM_S5)
 }
 
 /// Immediate Compare Signed Less Than
@@ -3290,14 +3170,10 @@ pub unsafe fn __msa_clti_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clti_s.h, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clti_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_clti_s_h(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clti_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_clti_s_h(a, IMM_S5)
 }
 
 /// Immediate Compare Signed Less Than
@@ -3310,14 +3186,10 @@ pub unsafe fn __msa_clti_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clti_s.w, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clti_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_clti_s_w(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clti_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_clti_s_w(a, IMM_S5)
 }
 
 /// Immediate Compare Signed Less Than
@@ -3330,14 +3202,10 @@ pub unsafe fn __msa_clti_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clti_s.d, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clti_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_clti_s_d(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clti_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_clti_s_d(a, IMM_S5)
 }
 
 /// Immediate Compare Unsigned Less Than
@@ -3350,14 +3218,10 @@ pub unsafe fn __msa_clti_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clti_u.b, imm5 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clti_u_b(a: v16u8, imm5: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_clti_u_b(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clti_u_b<const IMM5: i32>(a: v16u8) -> v16i8 {
+    static_assert_imm5!(IMM5);
+    msa_clti_u_b(a, IMM5)
 }
 
 /// Immediate Compare Unsigned Less Than
@@ -3370,14 +3234,10 @@ pub unsafe fn __msa_clti_u_b(a: v16u8, imm5: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clti_u.h, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clti_u_h(a: v8u16, imm5: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_clti_u_h(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clti_u_h<const IMM5: i32>(a: v8u16) -> v8i16 {
+    static_assert_imm5!(IMM5);
+    msa_clti_u_h(a, IMM5)
 }
 
 /// Immediate Compare Unsigned Less Than
@@ -3390,14 +3250,10 @@ pub unsafe fn __msa_clti_u_h(a: v8u16, imm5: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clti_u.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clti_u_w(a: v4u32, imm5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_clti_u_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clti_u_w<const IMM5: i32>(a: v4u32) -> v4i32 {
+    static_assert_imm5!(IMM5);
+    msa_clti_u_w(a, IMM5)
 }
 
 /// Immediate Compare Unsigned Less Than
@@ -3410,14 +3266,10 @@ pub unsafe fn __msa_clti_u_w(a: v4u32, imm5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(clti_u.d, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_clti_u_d(a: v2u64, imm5: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_clti_u_d(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_clti_u_d<const IMM5: i32>(a: v2u64) -> v2i64 {
+    static_assert_imm5!(IMM5);
+    msa_clti_u_d(a, IMM5)
 }
 
 /// Element Copy to GPR Signed
@@ -3428,14 +3280,10 @@ pub unsafe fn __msa_clti_u_d(a: v2u64, imm5: i32) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(copy_s.b, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_copy_s_b(a: v16i8, imm4: i32) -> i32 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_copy_s_b(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_copy_s_b<const IMM4: i32>(a: v16i8) -> i32 {
+    static_assert_imm4!(IMM4);
+    msa_copy_s_b(a, IMM4)
 }
 
 /// Element Copy to GPR Signed
@@ -3446,14 +3294,10 @@ pub unsafe fn __msa_copy_s_b(a: v16i8, imm4: i32) -> i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(copy_s.h, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_copy_s_h(a: v8i16, imm3: i32) -> i32 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_copy_s_h(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_copy_s_h<const IMM3: i32>(a: v8i16) -> i32 {
+    static_assert_imm3!(IMM3);
+    msa_copy_s_h(a, IMM3)
 }
 
 /// Element Copy to GPR Signed
@@ -3464,14 +3308,10 @@ pub unsafe fn __msa_copy_s_h(a: v8i16, imm3: i32) -> i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(copy_s.w, imm2 = 0b11))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_copy_s_w(a: v4i32, imm2: i32) -> i32 {
-    macro_rules! call {
-        ($imm2:expr) => {
-            msa_copy_s_w(a, $imm2)
-        };
-    }
-    constify_imm2!(imm2, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_copy_s_w<const IMM2: i32>(a: v4i32) -> i32 {
+    static_assert_imm2!(IMM2);
+    msa_copy_s_w(a, IMM2)
 }
 
 /// Element Copy to GPR Signed
@@ -3482,14 +3322,10 @@ pub unsafe fn __msa_copy_s_w(a: v4i32, imm2: i32) -> i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(copy_s.d, imm1 = 0b1))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_copy_s_d(a: v2i64, imm1: i32) -> i64 {
-    macro_rules! call {
-        ($imm1:expr) => {
-            msa_copy_s_d(a, $imm1)
-        };
-    }
-    constify_imm1!(imm1, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_copy_s_d<const IMM1: i32>(a: v2i64) -> i64 {
+    static_assert_imm1!(IMM1);
+    msa_copy_s_d(a, IMM1)
 }
 
 /// Element Copy to GPR Unsigned
@@ -3500,14 +3336,10 @@ pub unsafe fn __msa_copy_s_d(a: v2i64, imm1: i32) -> i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(copy_u.b, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_copy_u_b(a: v16i8, imm4: i32) -> u32 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_copy_u_b(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_copy_u_b<const IMM4: i32>(a: v16i8) -> u32 {
+    static_assert_imm4!(IMM4);
+    msa_copy_u_b(a, IMM4)
 }
 
 /// Element Copy to GPR Unsigned
@@ -3518,14 +3350,10 @@ pub unsafe fn __msa_copy_u_b(a: v16i8, imm4: i32) -> u32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(copy_u.h, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_copy_u_h(a: v8i16, imm3: i32) -> u32 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_copy_u_h(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_copy_u_h<const IMM3: i32>(a: v8i16) -> u32 {
+    static_assert_imm3!(IMM3);
+    msa_copy_u_h(a, IMM3)
 }
 
 /// Element Copy to GPR Unsigned
@@ -3536,14 +3364,10 @@ pub unsafe fn __msa_copy_u_h(a: v8i16, imm3: i32) -> u32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(copy_u.w, imm2 = 0b11))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_copy_u_w(a: v4i32, imm2: i32) -> u32 {
-    macro_rules! call {
-        ($imm2:expr) => {
-            msa_copy_u_w(a, $imm2)
-        };
-    }
-    constify_imm2!(imm2, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_copy_u_w<const IMM2: i32>(a: v4i32) -> u32 {
+    static_assert_imm2!(IMM2);
+    msa_copy_u_w(a, IMM2)
 }
 
 /// Element Copy to GPR Unsigned
@@ -3554,14 +3378,10 @@ pub unsafe fn __msa_copy_u_w(a: v4i32, imm2: i32) -> u32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(copy_u.d, imm1 = 0b1))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_copy_u_d(a: v2i64, imm1: i32) -> u64 {
-    macro_rules! call {
-        ($imm1:expr) => {
-            msa_copy_u_d(a, $imm1)
-        };
-    }
-    constify_imm1!(imm1, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_copy_u_d<const IMM1: i32>(a: v2i64) -> u64 {
+    static_assert_imm1!(IMM1);
+    msa_copy_u_d(a, IMM1)
 }
 
 /// GPR Copy to MSA Control Register
@@ -5790,14 +5610,10 @@ pub unsafe fn __msa_ilvr_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(insert.b, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_insert_b(a: v16i8, imm4: i32, c: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_insert_b(a, $imm4, c)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_insert_b<const IMM4: i32>(a: v16i8, c: i32) -> v16i8 {
+    static_assert_imm4!(IMM4);
+    msa_insert_b(a, IMM4, c)
 }
 
 /// GPR Insert Element
@@ -5809,14 +5625,10 @@ pub unsafe fn __msa_insert_b(a: v16i8, imm4: i32, c: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(insert.h, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_insert_h(a: v8i16, imm3: i32, c: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_insert_h(a, $imm3, c)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_insert_h<const IMM3: i32>(a: v8i16, c: i32) -> v8i16 {
+    static_assert_imm3!(IMM3);
+    msa_insert_h(a, IMM3, c)
 }
 
 /// GPR Insert Element
@@ -5828,14 +5640,10 @@ pub unsafe fn __msa_insert_h(a: v8i16, imm3: i32, c: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(insert.w, imm2 = 0b11))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_insert_w(a: v4i32, imm2: i32, c: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm2:expr) => {
-            msa_insert_w(a, $imm2, c)
-        };
-    }
-    constify_imm2!(imm2, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_insert_w<const IMM2: i32>(a: v4i32, c: i32) -> v4i32 {
+    static_assert_imm2!(IMM2);
+    msa_insert_w(a, IMM2, c)
 }
 
 /// GPR Insert Element
@@ -5847,14 +5655,10 @@ pub unsafe fn __msa_insert_w(a: v4i32, imm2: i32, c: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(insert.d, imm1 = 0b1))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_insert_d(a: v2i64, imm1: i32, c: i64) -> v2i64 {
-    macro_rules! call {
-        ($imm1:expr) => {
-            msa_insert_d(a, $imm1, c)
-        };
-    }
-    constify_imm1!(imm1, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_insert_d<const IMM1: i32>(a: v2i64, c: i64) -> v2i64 {
+    static_assert_imm1!(IMM1);
+    msa_insert_d(a, IMM1, c)
 }
 
 /// Element Insert Element
@@ -5866,14 +5670,10 @@ pub unsafe fn __msa_insert_d(a: v2i64, imm1: i32, c: i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(insve.b, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_insve_b(a: v16i8, imm4: i32, c: v16i8) -> v16i8 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_insve_b(a, $imm4, c)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_insve_b<const IMM4: i32>(a: v16i8, c: v16i8) -> v16i8 {
+    static_assert_imm4!(IMM4);
+    msa_insve_b(a, IMM4, c)
 }
 
 /// Element Insert Element
@@ -5885,14 +5685,10 @@ pub unsafe fn __msa_insve_b(a: v16i8, imm4: i32, c: v16i8) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(insve.h, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_insve_h(a: v8i16, imm3: i32, c: v8i16) -> v8i16 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_insve_h(a, $imm3, c)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_insve_h<const IMM3: i32>(a: v8i16, c: v8i16) -> v8i16 {
+    static_assert_imm3!(IMM3);
+    msa_insve_h(a, IMM3, c)
 }
 
 /// Element Insert Element
@@ -5904,14 +5700,10 @@ pub unsafe fn __msa_insve_h(a: v8i16, imm3: i32, c: v8i16) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(insve.w, imm2 = 0b11))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_insve_w(a: v4i32, imm2: i32, c: v4i32) -> v4i32 {
-    macro_rules! call {
-        ($imm2:expr) => {
-            msa_insve_w(a, $imm2, c)
-        };
-    }
-    constify_imm2!(imm2, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_insve_w<const IMM2: i32>(a: v4i32, c: v4i32) -> v4i32 {
+    static_assert_imm2!(IMM2);
+    msa_insve_w(a, IMM2, c)
 }
 
 /// Element Insert Element
@@ -5923,14 +5715,10 @@ pub unsafe fn __msa_insve_w(a: v4i32, imm2: i32, c: v4i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(insve.d, imm1 = 0b1))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_insve_d(a: v2i64, imm1: i32, c: v2i64) -> v2i64 {
-    macro_rules! call {
-        ($imm1:expr) => {
-            msa_insve_d(a, $imm1, c)
-        };
-    }
-    constify_imm1!(imm1, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_insve_d<const IMM1: i32>(a: v2i64, c: v2i64) -> v2i64 {
+    static_assert_imm1!(IMM1);
+    msa_insve_d(a, IMM1, c)
 }
 
 /// Vector Load
@@ -5942,14 +5730,10 @@ pub unsafe fn __msa_insve_d(a: v2i64, imm1: i32, c: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(ld.b, imm_s10 = 0b1111111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_ld_b(mem_addr: *mut u8, imm_s10: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm_s10:expr) => {
-            msa_ld_b(mem_addr, $imm_s10)
-        };
-    }
-    constify_imm_s10!(imm_s10, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_ld_b<const IMM_S10: i32>(mem_addr: *mut u8) -> v16i8 {
+    static_assert_imm_s10!(IMM_S10);
+    msa_ld_b(mem_addr, IMM_S10)
 }
 
 /// Vector Load
@@ -5961,14 +5745,11 @@ pub unsafe fn __msa_ld_b(mem_addr: *mut u8, imm_s10: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(ld.h, imm_s11 = 0b11111111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_ld_h(mem_addr: *mut u8, imm_s11: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm_s11:expr) => {
-            msa_ld_h(mem_addr, $imm_s11)
-        };
-    }
-    constify_imm_s11!(imm_s11, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_ld_h<const IMM_S11: i32>(mem_addr: *mut u8) -> v8i16 {
+    static_assert_imm_s11!(IMM_S11);
+    static_assert!(IMM_S11: i32 where IMM_S11 % 2 == 0);
+    msa_ld_h(mem_addr, IMM_S11)
 }
 
 /// Vector Load
@@ -5980,14 +5761,11 @@ pub unsafe fn __msa_ld_h(mem_addr: *mut u8, imm_s11: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(ld.w, imm_s12 = 0b111111111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_ld_w(mem_addr: *mut u8, imm_s12: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm_s12:expr) => {
-            msa_ld_w(mem_addr, $imm_s12)
-        };
-    }
-    constify_imm_s12!(imm_s12, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_ld_w<const IMM_S12: i32>(mem_addr: *mut u8) -> v4i32 {
+    static_assert_imm_s12!(IMM_S12);
+    static_assert!(IMM_S12: i32 where IMM_S12 % 4 == 0);
+    msa_ld_w(mem_addr, IMM_S12)
 }
 
 /// Vector Load
@@ -5999,14 +5777,11 @@ pub unsafe fn __msa_ld_w(mem_addr: *mut u8, imm_s12: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(ld.d, imm_s13 = 0b1111111111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_ld_d(mem_addr: *mut u8, imm_s13: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm_s13:expr) => {
-            msa_ld_d(mem_addr, $imm_s13)
-        };
-    }
-    constify_imm_s13!(imm_s13, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_ld_d<const IMM_S13: i32>(mem_addr: *mut u8) -> v2i64 {
+    static_assert_imm_s13!(IMM_S13);
+    static_assert!(IMM_S13: i32 where IMM_S13 % 8 == 0);
+    msa_ld_d(mem_addr, IMM_S13)
 }
 
 /// Immediate Load
@@ -6354,14 +6129,10 @@ pub unsafe fn __msa_max_u_d(a: v2u64, b: v2u64) -> v2u64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(maxi_s.b, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_maxi_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_maxi_s_b(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_maxi_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_maxi_s_b(a, IMM_S5)
 }
 
 /// Immediate Signed Maximum
@@ -6373,14 +6144,10 @@ pub unsafe fn __msa_maxi_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(maxi_s.h, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_maxi_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_maxi_s_h(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_maxi_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_maxi_s_h(a, IMM_S5)
 }
 
 /// Immediate Signed Maximum
@@ -6392,14 +6159,10 @@ pub unsafe fn __msa_maxi_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(maxi_s.w, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_maxi_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_maxi_s_w(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_maxi_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_maxi_s_w(a, IMM_S5)
 }
 
 /// Immediate Signed Maximum
@@ -6411,14 +6174,10 @@ pub unsafe fn __msa_maxi_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(maxi_s.d, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_maxi_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_maxi_s_d(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_maxi_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_maxi_s_d(a, IMM_S5)
 }
 
 /// Immediate Unsigned Maximum
@@ -6430,14 +6189,10 @@ pub unsafe fn __msa_maxi_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(maxi_u.b, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_maxi_u_b(a: v16u8, imm5: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_maxi_u_b(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_maxi_u_b<const IMM5: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm5!(IMM5);
+    msa_maxi_u_b(a, IMM5)
 }
 
 /// Immediate Unsigned Maximum
@@ -6449,14 +6204,10 @@ pub unsafe fn __msa_maxi_u_b(a: v16u8, imm5: i32) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(maxi_u.h, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_maxi_u_h(a: v8u16, imm5: i32) -> v8u16 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_maxi_u_h(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_maxi_u_h<const IMM5: i32>(a: v8u16) -> v8u16 {
+    static_assert_imm5!(IMM5);
+    msa_maxi_u_h(a, IMM5)
 }
 
 /// Immediate Unsigned Maximum
@@ -6468,14 +6219,10 @@ pub unsafe fn __msa_maxi_u_h(a: v8u16, imm5: i32) -> v8u16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(maxi_u.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_maxi_u_w(a: v4u32, imm5: i32) -> v4u32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_maxi_u_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_maxi_u_w<const IMM5: i32>(a: v4u32) -> v4u32 {
+    static_assert_imm5!(IMM5);
+    msa_maxi_u_w(a, IMM5)
 }
 
 /// Immediate Unsigned Maximum
@@ -6487,14 +6234,10 @@ pub unsafe fn __msa_maxi_u_w(a: v4u32, imm5: i32) -> v4u32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(maxi_u.d, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_maxi_u_d(a: v2u64, imm5: i32) -> v2u64 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_maxi_u_d(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_maxi_u_d<const IMM5: i32>(a: v2u64) -> v2u64 {
+    static_assert_imm5!(IMM5);
+    msa_maxi_u_d(a, IMM5)
 }
 
 /// Vector Minimum Based on Absolute Value
@@ -6614,14 +6357,10 @@ pub unsafe fn __msa_min_s_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(mini_s.b, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_mini_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_mini_s_b(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_mini_s_b<const IMM_S5: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_mini_s_b(a, IMM_S5)
 }
 
 /// Immediate Signed Minimum
@@ -6633,14 +6372,10 @@ pub unsafe fn __msa_mini_s_b(a: v16i8, imm_s5: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(mini_s.h, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_mini_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_mini_s_h(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_mini_s_h<const IMM_S5: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_mini_s_h(a, IMM_S5)
 }
 
 /// Immediate Signed Minimum
@@ -6652,14 +6387,10 @@ pub unsafe fn __msa_mini_s_h(a: v8i16, imm_s5: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(mini_s.w, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_mini_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_mini_s_w(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_mini_s_w<const IMM_S5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_mini_s_w(a, IMM_S5)
 }
 
 /// Immediate Signed Minimum
@@ -6671,14 +6402,10 @@ pub unsafe fn __msa_mini_s_w(a: v4i32, imm_s5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(mini_s.d, imm_s5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_mini_s_d(a: v2i64, imm_s5: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm_s5:expr) => {
-            msa_mini_s_d(a, $imm_s5)
-        };
-    }
-    constify_imm_s5!(imm_s5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_mini_s_d<const IMM_S5: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm_s5!(IMM_S5);
+    msa_mini_s_d(a, IMM_S5)
 }
 
 /// Vector Unsigned Minimum
@@ -6742,14 +6469,10 @@ pub unsafe fn __msa_min_u_d(a: v2u64, b: v2u64) -> v2u64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(mini_u.b, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_mini_u_b(a: v16u8, imm5: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_mini_u_b(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_mini_u_b<const IMM5: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm5!(IMM5);
+    msa_mini_u_b(a, IMM5)
 }
 
 /// Immediate Unsigned Minimum
@@ -6761,14 +6484,10 @@ pub unsafe fn __msa_mini_u_b(a: v16u8, imm5: i32) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(mini_u.h, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_mini_u_h(a: v8u16, imm5: i32) -> v8u16 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_mini_u_h(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_mini_u_h<const IMM5: i32>(a: v8u16) -> v8u16 {
+    static_assert_imm5!(IMM5);
+    msa_mini_u_h(a, IMM5)
 }
 
 /// Immediate Unsigned Minimum
@@ -6780,14 +6499,10 @@ pub unsafe fn __msa_mini_u_h(a: v8u16, imm5: i32) -> v8u16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(mini_u.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_mini_u_w(a: v4u32, imm5: i32) -> v4u32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_mini_u_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_mini_u_w<const IMM5: i32>(a: v4u32) -> v4u32 {
+    static_assert_imm5!(IMM5);
+    msa_mini_u_w(a, IMM5)
 }
 
 /// Immediate Unsigned Minimum
@@ -6799,14 +6514,10 @@ pub unsafe fn __msa_mini_u_w(a: v4u32, imm5: i32) -> v4u32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(mini_u.d, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_mini_u_d(a: v2u64, imm5: i32) -> v2u64 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_mini_u_d(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_mini_u_d<const IMM5: i32>(a: v2u64) -> v2u64 {
+    static_assert_imm5!(IMM5);
+    msa_mini_u_d(a, IMM5)
 }
 
 /// Vector Signed Modulo
@@ -7289,14 +7000,10 @@ pub unsafe fn __msa_nor_v(a: v16u8, b: v16u8) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(nori.b, imm8 = 0b11111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_nori_b(a: v16u8, imm8: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm8:expr) => {
-            msa_nori_b(a, $imm8)
-        };
-    }
-    constify_imm8!(imm8, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_nori_b<const IMM8: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm8!(IMM8);
+    msa_nori_b(a, IMM8)
 }
 
 /// Vector Logical Or
@@ -7323,14 +7030,10 @@ pub unsafe fn __msa_or_v(a: v16u8, b: v16u8) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(ori.b, imm8 = 0b11111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_ori_b(a: v16u8, imm8: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm8:expr) => {
-            msa_ori_b(a, $imm8)
-        };
-    }
-    constify_imm8!(imm8, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_ori_b<const IMM8: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm8!(IMM8);
+    msa_ori_b(a, IMM8)
 }
 
 /// Vector Pack Even
@@ -7494,14 +7197,10 @@ pub unsafe fn __msa_pcnt_d(a: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(sat_s.b, imm4 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_sat_s_b(a: v16i8, imm3: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_sat_s_b(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_sat_s_b<const IMM3: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm3!(IMM3);
+    msa_sat_s_b(a, IMM3)
 }
 
 /// Immediate Signed Saturate
@@ -7513,14 +7212,10 @@ pub unsafe fn __msa_sat_s_b(a: v16i8, imm3: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(sat_s.h, imm3 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_sat_s_h(a: v8i16, imm4: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_sat_s_h(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_sat_s_h<const IMM4: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm4!(IMM4);
+    msa_sat_s_h(a, IMM4)
 }
 
 /// Immediate Signed Saturate
@@ -7532,14 +7227,10 @@ pub unsafe fn __msa_sat_s_h(a: v8i16, imm4: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(sat_s.w, imm2 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_sat_s_w(a: v4i32, imm5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_sat_s_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_sat_s_w<const IMM5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm5!(IMM5);
+    msa_sat_s_w(a, IMM5)
 }
 
 /// Immediate Signed Saturate
@@ -7551,14 +7242,10 @@ pub unsafe fn __msa_sat_s_w(a: v4i32, imm5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(sat_s.d, imm1 = 0b111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_sat_s_d(a: v2i64, imm6: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm6:expr) => {
-            msa_sat_s_d(a, $imm6)
-        };
-    }
-    constify_imm6!(imm6, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_sat_s_d<const IMM6: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm6!(IMM6);
+    msa_sat_s_d(a, IMM6)
 }
 
 /// Immediate Unsigned Saturate
@@ -7570,14 +7257,10 @@ pub unsafe fn __msa_sat_s_d(a: v2i64, imm6: i32) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(sat_u.b, imm4 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_sat_u_b(a: v16u8, imm3: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_sat_u_b(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_sat_u_b<const IMM3: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm3!(IMM3);
+    msa_sat_u_b(a, IMM3)
 }
 
 /// Immediate Unsigned Saturate
@@ -7589,14 +7272,10 @@ pub unsafe fn __msa_sat_u_b(a: v16u8, imm3: i32) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(sat_u.h, imm3 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_sat_u_h(a: v8u16, imm4: i32) -> v8u16 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_sat_u_h(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_sat_u_h<const IMM4: i32>(a: v8u16) -> v8u16 {
+    static_assert_imm4!(IMM4);
+    msa_sat_u_h(a, IMM4)
 }
 
 /// Immediate Unsigned Saturate
@@ -7608,14 +7287,10 @@ pub unsafe fn __msa_sat_u_h(a: v8u16, imm4: i32) -> v8u16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(sat_u.w, imm2 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_sat_u_w(a: v4u32, imm5: i32) -> v4u32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_sat_u_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_sat_u_w<const IMM5: i32>(a: v4u32) -> v4u32 {
+    static_assert_imm5!(IMM5);
+    msa_sat_u_w(a, IMM5)
 }
 
 /// Immediate Unsigned Saturate
@@ -7627,14 +7302,10 @@ pub unsafe fn __msa_sat_u_w(a: v4u32, imm5: i32) -> v4u32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(sat_u.d, imm1 = 0b111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_sat_u_d(a: v2u64, imm6: i32) -> v2u64 {
-    macro_rules! call {
-        ($imm6:expr) => {
-            msa_sat_u_d(a, $imm6)
-        };
-    }
-    constify_imm6!(imm6, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_sat_u_d<const IMM6: i32>(a: v2u64) -> v2u64 {
+    static_assert_imm6!(IMM6);
+    msa_sat_u_d(a, IMM6)
 }
 
 /// Immediate Set Shuffle Elements
@@ -7647,14 +7318,10 @@ pub unsafe fn __msa_sat_u_d(a: v2u64, imm6: i32) -> v2u64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(shf.b, imm8 = 0b11111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_shf_b(a: v16i8, imm8: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm8:expr) => {
-            msa_shf_b(a, $imm8)
-        };
-    }
-    constify_imm8!(imm8, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_shf_b<const IMM8: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm8!(IMM8);
+    msa_shf_b(a, IMM8)
 }
 
 /// Immediate Set Shuffle Elements
@@ -7667,14 +7334,10 @@ pub unsafe fn __msa_shf_b(a: v16i8, imm8: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(shf.h, imm8 = 0b11111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_shf_h(a: v8i16, imm8: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm8:expr) => {
-            msa_shf_h(a, $imm8)
-        };
-    }
-    constify_imm8!(imm8, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_shf_h<const IMM8: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm8!(IMM8);
+    msa_shf_h(a, IMM8)
 }
 
 /// Immediate Set Shuffle Elements
@@ -7687,14 +7350,10 @@ pub unsafe fn __msa_shf_h(a: v8i16, imm8: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(shf.w, imm8 = 0b11111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_shf_w(a: v4i32, imm8: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm8:expr) => {
-            msa_shf_w(a, $imm8)
-        };
-    }
-    constify_imm8!(imm8, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_shf_w<const IMM8: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm8!(IMM8);
+    msa_shf_w(a, IMM8)
 }
 
 /// GPR Columns Slide
@@ -7938,14 +7597,10 @@ pub unsafe fn __msa_sll_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(slli.b, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_slli_b(a: v16i8, imm4: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_slli_b(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_slli_b<const IMM4: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm4!(IMM4);
+    msa_slli_b(a, IMM4)
 }
 
 /// Immediate Shift Left
@@ -7957,14 +7612,10 @@ pub unsafe fn __msa_slli_b(a: v16i8, imm4: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(slli.h, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_slli_h(a: v8i16, imm3: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_slli_h(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_slli_h<const IMM3: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm3!(IMM3);
+    msa_slli_h(a, IMM3)
 }
 
 /// Immediate Shift Left
@@ -7976,14 +7627,10 @@ pub unsafe fn __msa_slli_h(a: v8i16, imm3: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(slli.w, imm2 = 0b11))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_slli_w(a: v4i32, imm2: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm2:expr) => {
-            msa_slli_w(a, $imm2)
-        };
-    }
-    constify_imm2!(imm2, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_slli_w<const IMM2: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm2!(IMM2);
+    msa_slli_w(a, IMM2)
 }
 
 /// Immediate Shift Left
@@ -7995,14 +7642,10 @@ pub unsafe fn __msa_slli_w(a: v4i32, imm2: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(slli.d, imm1 = 0b1))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_slli_d(a: v2i64, imm1: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm1:expr) => {
-            msa_slli_d(a, $imm1)
-        };
-    }
-    constify_imm1!(imm1, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_slli_d<const IMM1: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm1!(IMM1);
+    msa_slli_d(a, IMM1)
 }
 
 /// GPR Element Splat
@@ -8069,14 +7712,10 @@ pub unsafe fn __msa_splat_d(a: v2i64, b: i32) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(splati.b, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_splati_b(a: v16i8, imm4: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_splati_b(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_splati_b<const IMM4: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm4!(IMM4);
+    msa_splati_b(a, IMM4)
 }
 
 /// Immediate Element Splat
@@ -8087,14 +7726,10 @@ pub unsafe fn __msa_splati_b(a: v16i8, imm4: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(splati.h, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_splati_h(a: v8i16, imm3: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_splati_h(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_splati_h<const IMM3: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm3!(IMM3);
+    msa_splati_h(a, IMM3)
 }
 
 /// Immediate Element Splat
@@ -8105,14 +7740,10 @@ pub unsafe fn __msa_splati_h(a: v8i16, imm3: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(splati.w, imm2 = 0b11))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_splati_w(a: v4i32, imm2: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm2:expr) => {
-            msa_splati_w(a, $imm2)
-        };
-    }
-    constify_imm2!(imm2, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_splati_w<const IMM2: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm2!(IMM2);
+    msa_splati_w(a, IMM2)
 }
 
 /// Immediate Element Splat
@@ -8123,14 +7754,10 @@ pub unsafe fn __msa_splati_w(a: v4i32, imm2: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(splati.d, imm1 = 0b1))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_splati_d(a: v2i64, imm1: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm1:expr) => {
-            msa_splati_d(a, $imm1)
-        };
-    }
-    constify_imm1!(imm1, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_splati_d<const IMM1: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm1!(IMM1);
+    msa_splati_d(a, IMM1)
 }
 
 /// Vector Shift Right Arithmetic
@@ -8198,14 +7825,10 @@ pub unsafe fn __msa_sra_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srai.b, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srai_b(a: v16i8, imm3: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_srai_b(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srai_b<const IMM3: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm3!(IMM3);
+    msa_srai_b(a, IMM3)
 }
 
 /// Immediate Shift Right Arithmetic
@@ -8217,14 +7840,10 @@ pub unsafe fn __msa_srai_b(a: v16i8, imm3: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srai.h, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srai_h(a: v8i16, imm4: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_srai_h(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srai_h<const IMM4: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm4!(IMM4);
+    msa_srai_h(a, IMM4)
 }
 
 /// Immediate Shift Right Arithmetic
@@ -8236,14 +7855,10 @@ pub unsafe fn __msa_srai_h(a: v8i16, imm4: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srai.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srai_w(a: v4i32, imm5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_srai_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srai_w<const IMM5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm5!(IMM5);
+    msa_srai_w(a, IMM5)
 }
 
 /// Immediate Shift Right Arithmetic
@@ -8255,14 +7870,10 @@ pub unsafe fn __msa_srai_w(a: v4i32, imm5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srai.d, imm6 = 0b111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srai_d(a: v2i64, imm6: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm6:expr) => {
-            msa_srai_d(a, $imm6)
-        };
-    }
-    constify_imm6!(imm6, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srai_d<const IMM6: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm6!(IMM6);
+    msa_srai_d(a, IMM6)
 }
 
 /// Vector Shift Right Arithmetic Rounded
@@ -8335,14 +7946,10 @@ pub unsafe fn __msa_srar_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srari.b, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srari_b(a: v16i8, imm3: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_srari_b(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srari_b<const IMM3: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm3!(IMM3);
+    msa_srari_b(a, IMM3)
 }
 
 /// Immediate Shift Right Arithmetic Rounded
@@ -8355,14 +7962,10 @@ pub unsafe fn __msa_srari_b(a: v16i8, imm3: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srari.h, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srari_h(a: v8i16, imm4: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_srari_h(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srari_h<const IMM4: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm4!(IMM4);
+    msa_srari_h(a, IMM4)
 }
 
 /// Immediate Shift Right Arithmetic Rounded
@@ -8375,14 +7978,10 @@ pub unsafe fn __msa_srari_h(a: v8i16, imm4: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srari.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srari_w(a: v4i32, imm5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_srari_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srari_w<const IMM5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm5!(IMM5);
+    msa_srari_w(a, IMM5)
 }
 
 /// Immediate Shift Right Arithmetic Rounded
@@ -8395,14 +7994,10 @@ pub unsafe fn __msa_srari_w(a: v4i32, imm5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srari.d, imm6 = 0b111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srari_d(a: v2i64, imm6: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm6:expr) => {
-            msa_srari_d(a, $imm6)
-        };
-    }
-    constify_imm6!(imm6, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srari_d<const IMM6: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm6!(IMM6);
+    msa_srari_d(a, IMM6)
 }
 
 /// Vector Shift Right Logical
@@ -8470,14 +8065,10 @@ pub unsafe fn __msa_srl_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srli.b, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srli_b(a: v16i8, imm4: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_srli_b(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srli_b<const IMM4: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm4!(IMM4);
+    msa_srli_b(a, IMM4)
 }
 
 /// Immediate Shift Right Logical
@@ -8489,14 +8080,10 @@ pub unsafe fn __msa_srli_b(a: v16i8, imm4: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srli.h, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srli_h(a: v8i16, imm3: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_srli_h(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srli_h<const IMM3: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm3!(IMM3);
+    msa_srli_h(a, IMM3)
 }
 
 /// Immediate Shift Right Logical
@@ -8508,14 +8095,10 @@ pub unsafe fn __msa_srli_h(a: v8i16, imm3: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srli.w, imm2 = 0b11))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srli_w(a: v4i32, imm2: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm2:expr) => {
-            msa_srli_w(a, $imm2)
-        };
-    }
-    constify_imm2!(imm2, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srli_w<const IMM2: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm2!(IMM2);
+    msa_srli_w(a, IMM2)
 }
 
 /// Immediate Shift Right Logical
@@ -8527,14 +8110,10 @@ pub unsafe fn __msa_srli_w(a: v4i32, imm2: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srli.d, imm1 = 0b1))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srli_d(a: v2i64, imm1: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm1:expr) => {
-            msa_srli_d(a, $imm1)
-        };
-    }
-    constify_imm1!(imm1, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srli_d<const IMM1: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm1!(IMM1);
+    msa_srli_d(a, IMM1)
 }
 
 /// Vector Shift Right Logical Rounded
@@ -8607,14 +8186,10 @@ pub unsafe fn __msa_srlr_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srlri.b, imm3 = 0b111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srlri_b(a: v16i8, imm3: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm3:expr) => {
-            msa_srlri_b(a, $imm3)
-        };
-    }
-    constify_imm3!(imm3, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srlri_b<const IMM3: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm3!(IMM3);
+    msa_srlri_b(a, IMM3)
 }
 
 /// Immediate Shift Right Logical Rounded
@@ -8627,14 +8202,10 @@ pub unsafe fn __msa_srlri_b(a: v16i8, imm3: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srlri.h, imm4 = 0b1111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srlri_h(a: v8i16, imm4: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm4:expr) => {
-            msa_srlri_h(a, $imm4)
-        };
-    }
-    constify_imm4!(imm4, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srlri_h<const IMM4: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm4!(IMM4);
+    msa_srlri_h(a, IMM4)
 }
 
 /// Immediate Shift Right Logical Rounded
@@ -8647,14 +8218,10 @@ pub unsafe fn __msa_srlri_h(a: v8i16, imm4: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srlri.w, imm5 = 0b11111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srlri_w(a: v4i32, imm5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_srlri_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srlri_w<const IMM5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm5!(IMM5);
+    msa_srlri_w(a, IMM5)
 }
 
 /// Immediate Shift Right Logical Rounded
@@ -8667,14 +8234,10 @@ pub unsafe fn __msa_srlri_w(a: v4i32, imm5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(srlri.d, imm6 = 0b111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_srlri_d(a: v2i64, imm6: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm6:expr) => {
-            msa_srlri_d(a, $imm6)
-        };
-    }
-    constify_imm6!(imm6, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_srlri_d<const IMM6: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm6!(IMM6);
+    msa_srlri_d(a, IMM6)
 }
 
 /// Vector Store
@@ -9038,14 +8601,10 @@ pub unsafe fn __msa_subv_d(a: v2i64, b: v2i64) -> v2i64 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(subvi.b, imm5 = 0b10111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_subvi_b(a: v16i8, imm5: i32) -> v16i8 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_subvi_b(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_subvi_b<const IMM5: i32>(a: v16i8) -> v16i8 {
+    static_assert_imm5!(IMM5);
+    msa_subvi_b(a, IMM5)
 }
 
 /// Immediate Subtract
@@ -9057,14 +8616,10 @@ pub unsafe fn __msa_subvi_b(a: v16i8, imm5: i32) -> v16i8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(subvi.h, imm5 = 0b10111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_subvi_h(a: v8i16, imm5: i32) -> v8i16 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_subvi_h(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_subvi_h<const IMM5: i32>(a: v8i16) -> v8i16 {
+    static_assert_imm5!(IMM5);
+    msa_subvi_h(a, IMM5)
 }
 
 /// Immediate Subtract
@@ -9076,14 +8631,10 @@ pub unsafe fn __msa_subvi_h(a: v8i16, imm5: i32) -> v8i16 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(subvi.w, imm5 = 0b10111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_subvi_w(a: v4i32, imm5: i32) -> v4i32 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_subvi_w(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_subvi_w<const IMM5: i32>(a: v4i32) -> v4i32 {
+    static_assert_imm5!(IMM5);
+    msa_subvi_w(a, IMM5)
 }
 
 /// Immediate Subtract
@@ -9095,14 +8646,10 @@ pub unsafe fn __msa_subvi_w(a: v4i32, imm5: i32) -> v4i32 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(subvi.d, imm5 = 0b10111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_subvi_d(a: v2i64, imm5: i32) -> v2i64 {
-    macro_rules! call {
-        ($imm5:expr) => {
-            msa_subvi_d(a, $imm5)
-        };
-    }
-    constify_imm5!(imm5, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_subvi_d<const IMM5: i32>(a: v2i64) -> v2i64 {
+    static_assert_imm5!(IMM5);
+    msa_subvi_d(a, IMM5)
 }
 
 /// Vector Data Preserving Shuffle
@@ -9197,14 +8744,10 @@ pub unsafe fn __msa_xor_v(a: v16u8, b: v16u8) -> v16u8 {
 #[inline]
 #[target_feature(enable = "msa")]
 #[cfg_attr(test, assert_instr(xori.b, imm8 = 0b11111111))]
-#[rustc_args_required_const(1)]
-pub unsafe fn __msa_xori_b(a: v16u8, imm8: i32) -> v16u8 {
-    macro_rules! call {
-        ($imm8:expr) => {
-            msa_xori_b(a, $imm8)
-        };
-    }
-    constify_imm8!(imm8, call)
+#[rustc_legacy_const_generics(1)]
+pub unsafe fn __msa_xori_b<const IMM8: i32>(a: v16u8) -> v16u8 {
+    static_assert_imm8!(IMM8);
+    msa_xori_b(a, IMM8)
 }
 
 #[cfg(test)]

From 0090621417cfb19d81d1d0e27ced961299240784 Mon Sep 17 00:00:00 2001
From: Lzu Tao <taolzu@gmail.com>
Date: Mon, 1 Mar 2021 13:14:14 +0700
Subject: [PATCH 3/4] mips: Removed unused macro

---
 crates/core_arch/src/mips/msa/macros.rs | 41 -------------------------
 1 file changed, 41 deletions(-)

diff --git a/crates/core_arch/src/mips/msa/macros.rs b/crates/core_arch/src/mips/msa/macros.rs
index c955cb817b..9c22e16862 100644
--- a/crates/core_arch/src/mips/msa/macros.rs
+++ b/crates/core_arch/src/mips/msa/macros.rs
@@ -4275,47 +4275,6 @@ macro_rules! constify_imm5 {
     };
 }
 
-//immediate value: -16:15
-macro_rules! constify_imm_s5 {
-    ($imm8:expr, $expand:ident) => {
-        #[allow(overflowing_literals)]
-        match ($imm8) & 0b1_1111 {
-            0 => $expand!(0),
-            1 => $expand!(1),
-            2 => $expand!(2),
-            3 => $expand!(3),
-            4 => $expand!(4),
-            5 => $expand!(5),
-            6 => $expand!(6),
-            7 => $expand!(7),
-            8 => $expand!(8),
-            9 => $expand!(9),
-            10 => $expand!(10),
-            11 => $expand!(11),
-            12 => $expand!(12),
-            13 => $expand!(13),
-            14 => $expand!(14),
-            16 => $expand!(-16),
-            17 => $expand!(-15),
-            18 => $expand!(-14),
-            19 => $expand!(-13),
-            20 => $expand!(-12),
-            21 => $expand!(-11),
-            22 => $expand!(-10),
-            23 => $expand!(-9),
-            24 => $expand!(-8),
-            25 => $expand!(-7),
-            26 => $expand!(-6),
-            27 => $expand!(-5),
-            28 => $expand!(-4),
-            29 => $expand!(-3),
-            30 => $expand!(-2),
-            31 => $expand!(-1),
-            _ => $expand!(15),
-        }
-    };
-}
-
 //immediate value: 0:15
 macro_rules! constify_imm4 {
     ($imm8:expr, $expand:ident) => {

From c6d43f6087a4b5e3bf2fc28d4602269d8c06da72 Mon Sep 17 00:00:00 2001
From: Amanieu d'Antras <amanieu@gmail.com>
Date: Fri, 5 Mar 2021 22:44:01 +0000
Subject: [PATCH 4/4] Update range bounds on static_assert_imm_s*

---
 crates/core_arch/src/mips/msa/macros.rs | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/crates/core_arch/src/mips/msa/macros.rs b/crates/core_arch/src/mips/msa/macros.rs
index 9c22e16862..4bdf2bb690 100644
--- a/crates/core_arch/src/mips/msa/macros.rs
+++ b/crates/core_arch/src/mips/msa/macros.rs
@@ -14,19 +14,19 @@ macro_rules! static_assert_imm_s10 {
 
 macro_rules! static_assert_imm_s11 {
     ($imm:ident) => {
-        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -1024, 1022>::VALID;
+        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -1024, 1023>::VALID;
     };
 }
 
 macro_rules! static_assert_imm_s12 {
     ($imm:ident) => {
-        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -2048, 2044>::VALID;
+        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -2048, 2047>::VALID;
     };
 }
 
 macro_rules! static_assert_imm_s13 {
     ($imm:ident) => {
-        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -4096, 4088>::VALID;
+        let _ = $crate::core_arch::macros::ValidateConstImm::<$imm, -4096, 4095>::VALID;
     };
 }