Skip to content
This repository was archived by the owner on Feb 5, 2019. It is now read-only.

Commit eb745dc

Browse files
committed
AArch64: use AddressingModes.h accessors for compare shifts
No functional change because "lsl #12" is actually encoded as 12, but one less bug if someone ever decides to change that for the giggles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243536 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent c3a9cb5 commit eb745dc

File tree

1 file changed

+5
-4
lines changed

1 file changed

+5
-4
lines changed

lib/Target/AArch64/AArch64ConditionOptimizer.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@
5959
//===----------------------------------------------------------------------===//
6060

6161
#include "AArch64.h"
62+
#include "MCTargetDesc/AArch64AddressingModes.h"
6263
#include "llvm/ADT/DepthFirstIterator.h"
6364
#include "llvm/ADT/SmallVector.h"
6465
#include "llvm/ADT/Statistic.h"
@@ -153,20 +154,20 @@ MachineInstr *AArch64ConditionOptimizer::findSuitableCompare(
153154
case AArch64::SUBSXri:
154155
// cmn is an alias for adds with a dead destination register.
155156
case AArch64::ADDSWri:
156-
case AArch64::ADDSXri:
157+
case AArch64::ADDSXri: {
158+
unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm());
157159
if (!I->getOperand(2).isImm()) {
158160
DEBUG(dbgs() << "Immediate of cmp is symbolic, " << *I << '\n');
159161
return nullptr;
160-
} else if (I->getOperand(2).getImm() << I->getOperand(3).getImm() >=
161-
0xfff) {
162+
} else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) {
162163
DEBUG(dbgs() << "Immediate of cmp may be out of range, " << *I << '\n');
163164
return nullptr;
164165
} else if (!MRI->use_empty(I->getOperand(0).getReg())) {
165166
DEBUG(dbgs() << "Destination of cmp is not dead, " << *I << '\n');
166167
return nullptr;
167168
}
168169
return I;
169-
170+
}
170171
// Prevent false positive case like:
171172
// cmp w19, #0
172173
// cinc w0, w19, gt

0 commit comments

Comments
 (0)