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Merge pull request #55 from androm3da/rustc/10.0-2020-02-05
[libunwind] add hexagon support
2 parents 887a77d + cf84e9a commit dc83e3c

9 files changed

+333
-1
lines changed

‎libunwind/include/__libunwind_config.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@
2323
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 32
2424
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
2525
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_SPARC 31
26+
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON 34
2627
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_RISCV 64
2728

2829
#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
@@ -82,6 +83,12 @@
8283
# define _LIBUNWIND_CONTEXT_SIZE 16
8384
# define _LIBUNWIND_CURSOR_SIZE 24
8485
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K
86+
# elif defined(__hexagon__)
87+
# define _LIBUNWIND_TARGET_HEXAGON 1
88+
// Values here change when : Registers.hpp - hexagon_thread_state_t change
89+
# define _LIBUNWIND_CONTEXT_SIZE 18
90+
# define _LIBUNWIND_CURSOR_SIZE 24
91+
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON
8592
# elif defined(__mips__)
8693
# if defined(_ABIO32) && _MIPS_SIM == _ABIO32
8794
# define _LIBUNWIND_TARGET_MIPS_O32 1
@@ -142,6 +149,7 @@
142149
# define _LIBUNWIND_TARGET_MIPS_O32 1
143150
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
144151
# define _LIBUNWIND_TARGET_SPARC 1
152+
# define _LIBUNWIND_TARGET_HEXAGON 1
145153
# define _LIBUNWIND_TARGET_RISCV 1
146154
# define _LIBUNWIND_CONTEXT_SIZE 167
147155
# define _LIBUNWIND_CURSOR_SIZE 179

‎libunwind/include/libunwind.h

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -832,6 +832,44 @@ enum {
832832
UNW_SPARC_I7 = 31,
833833
};
834834

835+
// Hexagon register numbers
836+
enum {
837+
UNW_HEXAGON_R0,
838+
UNW_HEXAGON_R1,
839+
UNW_HEXAGON_R2,
840+
UNW_HEXAGON_R3,
841+
UNW_HEXAGON_R4,
842+
UNW_HEXAGON_R5,
843+
UNW_HEXAGON_R6,
844+
UNW_HEXAGON_R7,
845+
UNW_HEXAGON_R8,
846+
UNW_HEXAGON_R9,
847+
UNW_HEXAGON_R10,
848+
UNW_HEXAGON_R11,
849+
UNW_HEXAGON_R12,
850+
UNW_HEXAGON_R13,
851+
UNW_HEXAGON_R14,
852+
UNW_HEXAGON_R15,
853+
UNW_HEXAGON_R16,
854+
UNW_HEXAGON_R17,
855+
UNW_HEXAGON_R18,
856+
UNW_HEXAGON_R19,
857+
UNW_HEXAGON_R20,
858+
UNW_HEXAGON_R21,
859+
UNW_HEXAGON_R22,
860+
UNW_HEXAGON_R23,
861+
UNW_HEXAGON_R24,
862+
UNW_HEXAGON_R25,
863+
UNW_HEXAGON_R26,
864+
UNW_HEXAGON_R27,
865+
UNW_HEXAGON_R28,
866+
UNW_HEXAGON_R29,
867+
UNW_HEXAGON_R30,
868+
UNW_HEXAGON_R31,
869+
UNW_HEXAGON_P3_0,
870+
UNW_HEXAGON_PC,
871+
};
872+
835873
// RISC-V registers. These match the DWARF register numbers defined by section
836874
// 4 of the RISC-V ELF psABI specification, which can be found at:
837875
//

‎libunwind/src/Registers.hpp

Lines changed: 182 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@ enum {
3434
REGISTERS_MIPS_O32,
3535
REGISTERS_MIPS_NEWABI,
3636
REGISTERS_SPARC,
37+
REGISTERS_HEXAGON,
3738
REGISTERS_RISCV,
3839
};
3940

@@ -3518,6 +3519,187 @@ inline const char *Registers_sparc::getRegisterName(int regNum) {
35183519
}
35193520
#endif // _LIBUNWIND_TARGET_SPARC
35203521

3522+
#if defined(_LIBUNWIND_TARGET_HEXAGON)
3523+
/// Registers_hexagon holds the register state of a thread in a Hexagon QDSP6
3524+
/// process.
3525+
class _LIBUNWIND_HIDDEN Registers_hexagon {
3526+
public:
3527+
Registers_hexagon();
3528+
Registers_hexagon(const void *registers);
3529+
3530+
bool validRegister(int num) const;
3531+
uint32_t getRegister(int num) const;
3532+
void setRegister(int num, uint32_t value);
3533+
bool validFloatRegister(int num) const;
3534+
double getFloatRegister(int num) const;
3535+
void setFloatRegister(int num, double value);
3536+
bool validVectorRegister(int num) const;
3537+
v128 getVectorRegister(int num) const;
3538+
void setVectorRegister(int num, v128 value);
3539+
const char *getRegisterName(int num);
3540+
void jumpto();
3541+
static int lastDwarfRegNum() { return _LIBUNWIND_HIGHEST_DWARF_REGISTER_HEXAGON; }
3542+
static int getArch() { return REGISTERS_HEXAGON; }
3543+
3544+
uint32_t getSP() const { return _registers.__r[UNW_HEXAGON_R29]; }
3545+
void setSP(uint32_t value) { _registers.__r[UNW_HEXAGON_R29] = value; }
3546+
uint32_t getIP() const { return _registers.__r[UNW_HEXAGON_PC]; }
3547+
void setIP(uint32_t value) { _registers.__r[UNW_HEXAGON_PC] = value; }
3548+
3549+
private:
3550+
struct hexagon_thread_state_t {
3551+
unsigned int __r[35];
3552+
};
3553+
3554+
hexagon_thread_state_t _registers;
3555+
};
3556+
3557+
inline Registers_hexagon::Registers_hexagon(const void *registers) {
3558+
static_assert((check_fit<Registers_hexagon, unw_context_t>::does_fit),
3559+
"hexagon registers do not fit into unw_context_t");
3560+
memcpy(&_registers, static_cast<const uint8_t *>(registers),
3561+
sizeof(_registers));
3562+
}
3563+
3564+
inline Registers_hexagon::Registers_hexagon() {
3565+
memset(&_registers, 0, sizeof(_registers));
3566+
}
3567+
3568+
inline bool Registers_hexagon::validRegister(int regNum) const {
3569+
if (regNum <= UNW_HEXAGON_R31)
3570+
return true;
3571+
return false;
3572+
}
3573+
3574+
inline uint32_t Registers_hexagon::getRegister(int regNum) const {
3575+
if (regNum >= UNW_HEXAGON_R0 && regNum <= UNW_HEXAGON_R31)
3576+
return _registers.__r[regNum - UNW_HEXAGON_R0];
3577+
3578+
switch (regNum) {
3579+
case UNW_REG_IP:
3580+
return _registers.__r[UNW_HEXAGON_PC];
3581+
case UNW_REG_SP:
3582+
return _registers.__r[UNW_HEXAGON_R29];
3583+
}
3584+
_LIBUNWIND_ABORT("unsupported hexagon register");
3585+
}
3586+
3587+
inline void Registers_hexagon::setRegister(int regNum, uint32_t value) {
3588+
if (regNum >= UNW_HEXAGON_R0 && regNum <= UNW_HEXAGON_R31) {
3589+
_registers.__r[regNum - UNW_HEXAGON_R0] = value;
3590+
return;
3591+
}
3592+
3593+
switch (regNum) {
3594+
case UNW_REG_IP:
3595+
_registers.__r[UNW_HEXAGON_PC] = value;
3596+
return;
3597+
case UNW_REG_SP:
3598+
_registers.__r[UNW_HEXAGON_R29] = value;
3599+
return;
3600+
}
3601+
_LIBUNWIND_ABORT("unsupported hexagon register");
3602+
}
3603+
3604+
inline bool Registers_hexagon::validFloatRegister(int /* regNum */) const {
3605+
return false;
3606+
}
3607+
3608+
inline double Registers_hexagon::getFloatRegister(int /* regNum */) const {
3609+
_LIBUNWIND_ABORT("hexagon float support not implemented");
3610+
}
3611+
3612+
inline void Registers_hexagon::setFloatRegister(int /* regNum */,
3613+
double /* value */) {
3614+
_LIBUNWIND_ABORT("hexagon float support not implemented");
3615+
}
3616+
3617+
inline bool Registers_hexagon::validVectorRegister(int /* regNum */) const {
3618+
return false;
3619+
}
3620+
3621+
inline v128 Registers_hexagon::getVectorRegister(int /* regNum */) const {
3622+
_LIBUNWIND_ABORT("hexagon vector support not implemented");
3623+
}
3624+
3625+
inline void Registers_hexagon::setVectorRegister(int /* regNum */, v128 /* value */) {
3626+
_LIBUNWIND_ABORT("hexagon vector support not implemented");
3627+
}
3628+
3629+
inline const char *Registers_hexagon::getRegisterName(int regNum) {
3630+
switch (regNum) {
3631+
case UNW_HEXAGON_R0:
3632+
return "r0";
3633+
case UNW_HEXAGON_R1:
3634+
return "r1";
3635+
case UNW_HEXAGON_R2:
3636+
return "r2";
3637+
case UNW_HEXAGON_R3:
3638+
return "r3";
3639+
case UNW_HEXAGON_R4:
3640+
return "r4";
3641+
case UNW_HEXAGON_R5:
3642+
return "r5";
3643+
case UNW_HEXAGON_R6:
3644+
return "r6";
3645+
case UNW_HEXAGON_R7:
3646+
return "r7";
3647+
case UNW_HEXAGON_R8:
3648+
return "r8";
3649+
case UNW_HEXAGON_R9:
3650+
return "r9";
3651+
case UNW_HEXAGON_R10:
3652+
return "r10";
3653+
case UNW_HEXAGON_R11:
3654+
return "r11";
3655+
case UNW_HEXAGON_R12:
3656+
return "r12";
3657+
case UNW_HEXAGON_R13:
3658+
return "r13";
3659+
case UNW_HEXAGON_R14:
3660+
return "r14";
3661+
case UNW_HEXAGON_R15:
3662+
return "r15";
3663+
case UNW_HEXAGON_R16:
3664+
return "r16";
3665+
case UNW_HEXAGON_R17:
3666+
return "r17";
3667+
case UNW_HEXAGON_R18:
3668+
return "r18";
3669+
case UNW_HEXAGON_R19:
3670+
return "r19";
3671+
case UNW_HEXAGON_R20:
3672+
return "r20";
3673+
case UNW_HEXAGON_R21:
3674+
return "r21";
3675+
case UNW_HEXAGON_R22:
3676+
return "r22";
3677+
case UNW_HEXAGON_R23:
3678+
return "r23";
3679+
case UNW_HEXAGON_R24:
3680+
return "r24";
3681+
case UNW_HEXAGON_R25:
3682+
return "r25";
3683+
case UNW_HEXAGON_R26:
3684+
return "r26";
3685+
case UNW_HEXAGON_R27:
3686+
return "r27";
3687+
case UNW_HEXAGON_R28:
3688+
return "r28";
3689+
case UNW_HEXAGON_R29:
3690+
return "r29";
3691+
case UNW_HEXAGON_R30:
3692+
return "r30";
3693+
case UNW_HEXAGON_R31:
3694+
return "r31";
3695+
default:
3696+
return "unknown register";
3697+
}
3698+
3699+
}
3700+
#endif // _LIBUNWIND_TARGET_HEXAGON
3701+
3702+
35213703
#if defined(_LIBUNWIND_TARGET_RISCV)
35223704
/// Registers_riscv holds the register state of a thread in a 64-bit RISC-V
35233705
/// process.

‎libunwind/src/UnwindCursor.hpp

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Original file line numberDiff line numberDiff line change
@@ -1123,6 +1123,12 @@ class UnwindCursor : public AbstractUnwindCursor{
11231123
}
11241124
#endif
11251125

1126+
#if defined (_LIBUNWIND_TARGET_HEXAGON)
1127+
compact_unwind_encoding_t dwarfEncoding(Registers_hexagon &) const {
1128+
return 0;
1129+
}
1130+
#endif
1131+
11261132
#if defined (_LIBUNWIND_TARGET_MIPS_O32)
11271133
compact_unwind_encoding_t dwarfEncoding(Registers_mips_o32 &) const {
11281134
return 0;

‎libunwind/src/UnwindRegistersRestore.S

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Original file line numberDiff line numberDiff line change
@@ -808,6 +808,48 @@ DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv)
808808
l.jr r9
809809
l.nop
810810

811+
#elif defined(__hexagon__)
812+
# On entry:
813+
# thread_state pointer is in r2
814+
DEFINE_LIBUNWIND_FUNCTION(_ZN9libunwind17Registers_hexagon6jumptoEv)
815+
#
816+
# void libunwind::Registers_hexagon::jumpto()
817+
#
818+
r8 = memw(r0+#32)
819+
r9 = memw(r0+#36)
820+
r10 = memw(r0+#40)
821+
r11 = memw(r0+#44)
822+
823+
r12 = memw(r0+#48)
824+
r13 = memw(r0+#52)
825+
r14 = memw(r0+#56)
826+
r15 = memw(r0+#60)
827+
828+
r16 = memw(r0+#64)
829+
r17 = memw(r0+#68)
830+
r18 = memw(r0+#72)
831+
r19 = memw(r0+#76)
832+
833+
r20 = memw(r0+#80)
834+
r21 = memw(r0+#84)
835+
r22 = memw(r0+#88)
836+
r23 = memw(r0+#92)
837+
838+
r24 = memw(r0+#96)
839+
r25 = memw(r0+#100)
840+
r26 = memw(r0+#104)
841+
r27 = memw(r0+#108)
842+
843+
r28 = memw(r0+#112)
844+
r29 = memw(r0+#116)
845+
r30 = memw(r0+#120)
846+
r31 = memw(r0+#132)
847+
848+
r1 = memw(r0+#128)
849+
c4 = r1 // Predicate register
850+
r1 = memw(r0+#4)
851+
r0 = memw(r0)
852+
jumpr r31
811853
#elif defined(__mips__) && defined(_ABIO32) && _MIPS_SIM == _ABIO32
812854

813855
//

‎libunwind/src/UnwindRegistersSave.S

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Original file line numberDiff line numberDiff line change
@@ -945,6 +945,52 @@ DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
945945
# zero epcr
946946
l.sw 132(r3), r0
947947

948+
#elif defined(__hexagon__)
949+
#
950+
# extern int unw_getcontext(unw_context_t* thread_state)
951+
#
952+
# On entry:
953+
# thread_state pointer is in r0
954+
#
955+
#define OFFSET(offset) (offset/4)
956+
DEFINE_LIBUNWIND_FUNCTION(__unw_getcontext)
957+
memw(r0+#32) = r8
958+
memw(r0+#36) = r9
959+
memw(r0+#40) = r10
960+
memw(r0+#44) = r11
961+
962+
memw(r0+#48) = r12
963+
memw(r0+#52) = r13
964+
memw(r0+#56) = r14
965+
memw(r0+#60) = r15
966+
967+
memw(r0+#64) = r16
968+
memw(r0+#68) = r17
969+
memw(r0+#72) = r18
970+
memw(r0+#76) = r19
971+
972+
memw(r0+#80) = r20
973+
memw(r0+#84) = r21
974+
memw(r0+#88) = r22
975+
memw(r0+#92) = r23
976+
977+
memw(r0+#96) = r24
978+
memw(r0+#100) = r25
979+
memw(r0+#104) = r26
980+
memw(r0+#108) = r27
981+
982+
memw(r0+#112) = r28
983+
memw(r0+#116) = r29
984+
memw(r0+#120) = r30
985+
memw(r0+#124) = r31
986+
r1 = c4 // Predicate register
987+
memw(r0+#128) = r1
988+
r1 = memw(r30) // *FP == Saved FP
989+
r1 = r31
990+
memw(r0+#132) = r1
991+
992+
jumpr r31
993+
948994
#elif defined(__sparc__)
949995

950996
#

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