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1 parent c3c80ad commit 72ef6d7Copy full SHA for 72ef6d7
llvm/test/CodeGen/X86/setcc.ll
@@ -338,3 +338,20 @@ define i32 @PR55138(i32 %x) {
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%and = and i32 %shr, 1
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ret i32 %and
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}
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+
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+; FIXME: Miscompile.
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+define i64 @pr63055(double %arg) {
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+; X86-LABEL: pr63055:
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+; X86: ## %bb.0:
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+; X86-NEXT: movl $255, %eax
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+; X86-NEXT: xorl %edx, %edx
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+; X86-NEXT: retl
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+;
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+; X64-LABEL: pr63055:
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+; X64: ## %bb.0:
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+; X64-NEXT: movl $255, %eax
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+; X64-NEXT: retq
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+ %fcmp = fcmp une double 0x7FF8000000000000, %arg
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+ %ext = zext i1 %fcmp to i64
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+ ret i64 %ext
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+}
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