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[X86] Add inline assembly load hardening mitigation for Load Value Injection (LVI)
Added code to X86AsmParser::emitInstruction() to add an LFENCE after each instruction that may load, and emit a warning if it encounters an instruction that may be vulnerable, but cannot be automatically mitigated. Differential Revision: https://reviews.llvm.org/D76158
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‎llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp

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@@ -31,6 +31,7 @@
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_ostream.h"
@@ -39,6 +40,11 @@
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using namespace llvm;
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static cl::opt<bool> LVIInlineAsmHardening(
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"x86-experimental-lvi-inline-asm-hardening",
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cl::desc("Harden inline assembly code that may be vulnerable to Load Value"
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" Injection (LVI). This feature is experimental."), cl::Hidden);
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static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
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if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
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ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
@@ -930,6 +936,11 @@ class X86AsmParser : public MCTargetAsmParser {
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bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
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bool processInstruction(MCInst &Inst, const OperandVector &Ops);
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// Load Value Injection (LVI) Mitigations for machine code
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void emitWarningForSpecialLVIInstruction(SMLoc Loc);
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bool applyLVICFIMitigation(MCInst &Inst);
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bool applyLVILoadHardeningMitigation(MCInst &Inst, MCStreamer &Out);
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/// Wrapper around MCStreamer::emitInstruction(). Possibly adds
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/// instrumentation around Inst.
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void emitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
@@ -3149,9 +3160,104 @@ bool X86AsmParser::validateInstruction(MCInst &Inst, const OperandVector &Ops) {
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31503161
static const char *getSubtargetFeatureName(uint64_t Val);
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void X86AsmParser::emitWarningForSpecialLVIInstruction(SMLoc Loc) {
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Warning(Loc, "Instruction may be vulnerable to LVI and "
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"requires manual mitigation");
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Note(SMLoc(), "See https://software.intel.com/"
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"security-software-guidance/insights/"
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"deep-dive-load-value-injection#specialinstructions"
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" for more information");
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}
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/// RET instructions and also instructions that indirect calls/jumps from memory
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/// combine a load and a branch within a single instruction. To mitigate these
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/// instructions against LVI, they must be decomposed into separate load and
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/// branch instructions, with an LFENCE in between. For more details, see:
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/// - X86LoadValueInjectionRetHardening.cpp
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/// - X86LoadValueInjectionIndirectThunks.cpp
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/// - https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
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///
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/// Returns `true` if a mitigation was applied or warning was emitted.
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bool X86AsmParser::applyLVICFIMitigation(MCInst &Inst) {
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// Information on control-flow instructions that require manual mitigation can
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// be found here:
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// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
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switch (Inst.getOpcode()) {
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case X86::RETW:
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case X86::RETL:
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case X86::RETQ:
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case X86::RETIL:
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case X86::RETIQ:
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case X86::RETIW:
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case X86::JMP16m:
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case X86::JMP32m:
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case X86::JMP64m:
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case X86::CALL16m:
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case X86::CALL32m:
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case X86::CALL64m:
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emitWarningForSpecialLVIInstruction(Inst.getLoc());
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return true;
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}
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return false;
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}
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/// To mitigate LVI, every instruction that performs a load can be followed by
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/// an LFENCE instruction to squash any potential mis-speculation. There are
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/// some instructions that require additional considerations, and may requre
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/// manual mitigation. For more details, see:
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/// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection
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///
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/// Returns `true` if a mitigation was applied or warning was emitted.
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bool X86AsmParser::applyLVILoadHardeningMitigation(MCInst &Inst,
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MCStreamer &Out) {
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auto Opcode = Inst.getOpcode();
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auto Flags = Inst.getFlags();
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if ((Flags & X86::IP_HAS_REPEAT) || (Flags & X86::IP_HAS_REPEAT_NE)) {
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// Information on REP string instructions that require manual mitigation can
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// be found here:
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// https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions
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switch (Opcode) {
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case X86::CMPSB:
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case X86::CMPSW:
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case X86::CMPSL:
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case X86::CMPSQ:
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case X86::SCASB:
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case X86::SCASW:
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case X86::SCASL:
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case X86::SCASQ:
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emitWarningForSpecialLVIInstruction(Inst.getLoc());
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return true;
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}
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} else if (Opcode == X86::REP_PREFIX || Opcode == X86::REPNE_PREFIX) {
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// If a REP instruction is found on its own line, it may or may not be
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// followed by a vulnerable instruction. Emit a warning just in case.
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emitWarningForSpecialLVIInstruction(Inst.getLoc());
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return true;
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}
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const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
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// LFENCE has the mayLoad property, don't double fence.
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if (MCID.mayLoad() && Inst.getOpcode() != X86::LFENCE) {
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MCInst FenceInst;
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FenceInst.setOpcode(X86::LFENCE);
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FenceInst.setLoc(Inst.getLoc());
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Out.emitInstruction(FenceInst, getSTI());
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return true;
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}
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return false;
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}
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void X86AsmParser::emitInstruction(MCInst &Inst, OperandVector &Operands,
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MCStreamer &Out) {
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Out.emitInstruction(Inst, getSTI());
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if (LVIInlineAsmHardening) {
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if (getSTI().getFeatureBits()[X86::FeatureLVIControlFlowIntegrity] &&
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applyLVICFIMitigation(Inst))
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return;
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if (getSTI().getFeatureBits()[X86::FeatureLVILoadHardening])
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applyLVILoadHardeningMitigation(Inst, Out);
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}
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}
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bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,

‎llvm/test/CodeGen/X86/lvi-hardening-inline-asm.ll

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@@ -0,0 +1,156 @@
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; RUN: llc -verify-machineinstrs -mtriple=x86_64-unknown -mattr=+lvi-load-hardening -mattr=+lvi-cfi -x86-experimental-lvi-inline-asm-hardening < %s -o %t.out 2> %t.err
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; RUN: FileCheck %s --check-prefix=X86 < %t.out
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; RUN: FileCheck %s --check-prefix=WARN < %t.err
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; Test module-level assembly
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module asm "pop %rbx"
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module asm "ret"
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; WARN: warning: Instruction may be vulnerable to LVI
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; WARN-NEXT: ret
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; WARN-NEXT: ^
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; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information
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; Function Attrs: noinline nounwind optnone uwtable
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define dso_local void @test_inline_asm() {
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entry:
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; X86-LABEL: test_inline_asm:
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call void asm sideeffect "mov 0x3fed(%rip),%rax", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: movq 16365(%rip), %rax
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; X86-NEXT: lfence
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call void asm sideeffect "movdqa 0x0(%rip),%xmm0", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: movdqa (%rip), %xmm0
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; X86-NEXT: lfence
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call void asm sideeffect "movslq 0x3e5d(%rip),%rbx", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: movslq 15965(%rip), %rbx
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; X86-NEXT: lfence
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call void asm sideeffect "mov (%r12,%rax,8),%rax", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: movq (%r12,%rax,8), %rax
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; X86-NEXT: lfence
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call void asm sideeffect "movq (24)(%rsi), %r11", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: movq 24(%rsi), %r11
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; X86-NEXT: lfence
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call void asm sideeffect "cmove %r12,%rax", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: cmoveq %r12, %rax
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; X86-NOT: lfence
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call void asm sideeffect "cmove (%r12),%rax", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: cmoveq (%r12), %rax
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; X86-NEXT: lfence
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call void asm sideeffect "pop %rbx", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: popq %rbx
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; X86-NEXT: lfence
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call void asm sideeffect "popq %rbx", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: popq %rbx
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; X86-NEXT: lfence
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call void asm sideeffect "xchg (%r12),%rax", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: xchgq %rax, (%r12)
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; X86-NEXT: lfence
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call void asm sideeffect "cmpxchg %r12,(%rax)", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: cmpxchgq %r12, (%rax)
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; X86-NEXT: lfence
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call void asm sideeffect "vpxor (%rcx,%rdx,1),%ymm1,%ymm0", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: vpxor (%rcx,%rdx), %ymm1, %ymm0
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; X86-NEXT: lfence
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call void asm sideeffect "vpmuludq 0x20(%rsi),%ymm0,%ymm12", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: vpmuludq 32(%rsi), %ymm0, %ymm12
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; X86-NEXT: lfence
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call void asm sideeffect "vpexpandq 0x40(%rdi),%zmm8{%k2}{z}", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: vpexpandq 64(%rdi), %zmm8 {%k2} {z}
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; X86-NEXT: lfence
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call void asm sideeffect "addq (%r12),%rax", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: addq (%r12), %rax
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; X86-NEXT: lfence
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call void asm sideeffect "subq Lpoly+0(%rip), %rax", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: subq Lpoly+0(%rip), %rax
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; X86-NEXT: lfence
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call void asm sideeffect "adcq %r12,(%rax)", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: adcq %r12, (%rax)
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; X86-NEXT: lfence
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call void asm sideeffect "negq (%rax)", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: negq (%rax)
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; X86-NEXT: lfence
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call void asm sideeffect "incq %rax", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: incq %rax
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; X86-NOT: lfence
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call void asm sideeffect "mulq (%rax)", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: mulq (%rax)
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; X86-NEXT: lfence
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call void asm sideeffect "imulq (%rax),%rdx", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: imulq (%rax), %rdx
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; X86-NEXT: lfence
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call void asm sideeffect "shlq $$1,(%rax)", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: shlq (%rax)
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; X86-NEXT: lfence
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call void asm sideeffect "shrq $$1,(%rax)", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: shrq (%rax)
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; X86-NEXT: lfence
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call void asm sideeffect "repz cmpsb %es:(%rdi),%ds:(%rsi)", "~{dirflag},~{fpsr},~{flags}"() #1
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; WARN: warning: Instruction may be vulnerable to LVI
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; WARN-NEXT: repz cmpsb %es:(%rdi),%ds:(%rsi)
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; WARN-NEXT: ^
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; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information
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; X86: rep cmpsb %es:(%rdi), %ds:(%rsi)
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; X86-NOT: lfence
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call void asm sideeffect "repnz scasb", "~{dirflag},~{fpsr},~{flags}"() #1
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; WARN: warning: Instruction may be vulnerable to LVI
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; WARN-NEXT: repnz scasb
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; WARN-NEXT: ^
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; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information
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; X86: repne scasb %es:(%rdi), %al
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; X86-NOT: lfence
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call void asm sideeffect "repnz", ""() #1
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; WARN: warning: Instruction may be vulnerable to LVI
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; WARN-NEXT: repnz
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; WARN-NEXT: ^
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; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information
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call void asm sideeffect "pinsrw $$0x6,(%eax),%xmm0", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: pinsrw $6, (%eax), %xmm0
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; X86-NEXT: lfence
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call void asm sideeffect "ret", "~{dirflag},~{fpsr},~{flags}"() #1
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; WARN: warning: Instruction may be vulnerable to LVI
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; WARN-NEXT: ret
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; WARN-NEXT: ^
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; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information
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; X86: retq
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; X86-NOT: lfence
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call void asm sideeffect "ret $$8", "~{dirflag},~{fpsr},~{flags}"() #1
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; WARN: warning: Instruction may be vulnerable to LVI
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; WARN-NEXT: ret $8
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; WARN-NEXT: ^
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; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information
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; X86: retq $8
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; X86-NOT: lfence
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call void asm sideeffect "jmpq *(%rdx)", "~{dirflag},~{fpsr},~{flags}"() #1
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; WARN: warning: Instruction may be vulnerable to LVI
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; WARN-NEXT: jmpq *(%rdx)
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; WARN-NEXT: ^
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; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information
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; X86: jmpq *(%rdx)
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; X86-NOT: lfence
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call void asm sideeffect "jmpq *0x100(%rdx)", "~{dirflag},~{fpsr},~{flags}"() #1
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; WARN: warning: Instruction may be vulnerable to LVI
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; WARN-NEXT: jmpq *0x100(%rdx)
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; WARN-NEXT: ^
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; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information
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; X86: jmpq *256(%rdx)
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; X86-NOT: lfence
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call void asm sideeffect "callq *200(%rdx)", "~{dirflag},~{fpsr},~{flags}"() #1
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; WARN: warning: Instruction may be vulnerable to LVI
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; WARN-NEXT: callq *200(%rdx)
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; WARN-NEXT: ^
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; WARN-NEXT: note: See https://software.intel.com/security-software-guidance/insights/deep-dive-load-value-injection#specialinstructions for more information
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; X86: callq *200(%rdx)
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; X86-NOT: lfence
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call void asm sideeffect "fldt 0x8(%rbp)", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: fldt 8(%rbp)
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; X86-NEXT: lfence
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call void asm sideeffect "fld %st(0)", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: fld %st(0)
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; X86-NOT: lfence
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; Test assembler macros
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call void asm sideeffect ".macro mplus1 x\0Aincq (\5Cx)\0A.endm\0Amplus1 %rcx", "~{dirflag},~{fpsr},~{flags}"() #1
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; X86: incq (%rcx)
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; X86-NEXT: lfence
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ret void
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}
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attributes #1 = { nounwind }

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