diff --git a/arch/arm/boot/dts/bcm2708-rpi.dtsi b/arch/arm/boot/dts/bcm2708-rpi.dtsi index 6a82591c51d19f..ce9795dad99f3b 100644 --- a/arch/arm/boot/dts/bcm2708-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2708-rpi.dtsi @@ -3,7 +3,7 @@ #include "bcm2835-rpi.dtsi" / { - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0>; }; @@ -102,6 +102,7 @@ }; &hdmi { + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; status = "disabled"; }; @@ -125,13 +126,23 @@ firmware = <&firmware>; }; +&sdhci { + pinctrl-names = "default"; + pinctrl-0 = <&emmc_gpio48>; + bus-width = <4>; +}; + sdhost_pins: &sdhost_gpio48 { /* Add alias */ }; &sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; brcm,overclock-50 = <0>; brcm,pio-limit = <1>; + status = "okay"; }; &cpu_thermal { diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts index 18c0f9599d3aaa..ccdc274665c093 100644 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts @@ -5,10 +5,10 @@ #include "bcm283x-rpi-csi1-2lane.dtsi" / { - compatible = "raspberrypi,4-model-b", "brcm,bcm2838"; + compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; model = "Raspberry Pi 4 Model B"; - memory { + memory@0 { device_type = "memory"; reg = <0x0 0x0 0x0>; }; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts index d1edd89b45f700..9024c6a7f5269d 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a-plus.dts @@ -100,6 +100,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -108,6 +110,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-a.dts b/arch/arm/boot/dts/bcm2835-rpi-a.dts index 1f2b9a1bf44ab8..4b1ca9e673e910 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-a.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-a.dts @@ -95,6 +95,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -103,6 +105,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts index eed015e55aeb8e..079558c245516e 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts @@ -102,6 +102,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -110,6 +112,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts index a94a5b8788860b..6613891cb2c4de 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts @@ -95,6 +95,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -103,6 +105,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts index a49bf6c96c062b..1cb79311642216 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-b.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts @@ -90,6 +90,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_HIGH>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -98,6 +100,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts index 4764a25585ab69..a75c882e65751f 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-cm1-io1.dts @@ -79,6 +79,15 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; }; &uart0 { diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts index b7f79f1c431ae4..aee17e9fd21caa 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero-w.dts @@ -113,12 +113,15 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &sdhci { #address-cells = <1>; #size-cells = <0>; pinctrl-0 = <&emmc_gpio34 &gpclk2_gpio43>; + bus-width = <4>; mmc-pwrseq = <&wifi_pwrseq>; non-removable; status = "okay"; @@ -129,6 +132,13 @@ }; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio32 &uart0_ctsrts_gpio30>; diff --git a/arch/arm/boot/dts/bcm2835-rpi-zero.dts b/arch/arm/boot/dts/bcm2835-rpi-zero.dts index eb5cfefb99b2a7..436a20d1e4c04f 100644 --- a/arch/arm/boot/dts/bcm2835-rpi-zero.dts +++ b/arch/arm/boot/dts/bcm2835-rpi-zero.dts @@ -103,6 +103,15 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; +}; + +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; }; &uart0 { diff --git a/arch/arm/boot/dts/bcm2835-rpi.dtsi b/arch/arm/boot/dts/bcm2835-rpi.dtsi index e8e16a919687aa..61e29b9e62f6b4 100644 --- a/arch/arm/boot/dts/bcm2835-rpi.dtsi +++ b/arch/arm/boot/dts/bcm2835-rpi.dtsi @@ -1,7 +1,7 @@ #include / { - memory { + memory@0 { device_type = "memory"; reg = <0 0x10000000>; }; @@ -19,8 +19,6 @@ soc { firmware: firmware { compatible = "raspberrypi,bcm2835-firmware", "simple-bus"; - #address-cells = <0>; - #size-cells = <0>; mboxes = <&mailbox>; }; @@ -86,19 +84,6 @@ status = "okay"; }; -&sdhci { - pinctrl-names = "default"; - pinctrl-0 = <&emmc_gpio48>; - bus-width = <4>; -}; - -&sdhost { - pinctrl-names = "default"; - pinctrl-0 = <&sdhost_gpio48>; - status = "okay"; - bus-width = <4>; -}; - &usb { power-domains = <&power RPI_POWER_DOMAIN_USB>; }; @@ -107,11 +92,6 @@ power-domains = <&power RPI_POWER_DOMAIN_V3D>; }; -&hdmi { - power-domains = <&power RPI_POWER_DOMAIN_HDMI>; - status = "okay"; -}; - &vec { power-domains = <&power RPI_POWER_DOMAIN_VEC>; status = "okay"; diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts index 8dbecffbd11094..3671064985dce8 100644 --- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts +++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts @@ -10,7 +10,7 @@ compatible = "raspberrypi,2-model-b", "brcm,bcm2836"; model = "Raspberry Pi 2 Model B"; - memory { + memory@0 { reg = <0 0x40000000>; }; @@ -40,6 +40,8 @@ &hdmi { hpd-gpios = <&gpio 46 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { @@ -48,6 +50,13 @@ status = "okay"; }; +&sdhost { + pinctrl-names = "default"; + pinctrl-0 = <&sdhost_gpio48>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_gpio14>; diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts index 42bb09044cc799..3d5f4ada9a2fab 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b-plus.dts @@ -14,7 +14,7 @@ stdout-path = "serial1:115200n8"; }; - memory { + memory@0 { reg = <0 0x40000000>; }; @@ -54,6 +54,8 @@ &hdmi { hpd-gpios = <&gpio 28 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; &pwm { diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts index ae968ebf95af8d..67c01b62b5884f 100644 --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts @@ -15,7 +15,7 @@ stdout-path = "serial1:115200n8"; }; - memory { + memory@0 { reg = <0 0x40000000>; }; @@ -56,6 +56,8 @@ &hdmi { hpd-gpios = <&expgpio 4 GPIO_ACTIVE_LOW>; + power-domains = <&power RPI_POWER_DOMAIN_HDMI>; + status = "okay"; }; /* uart0 communicates with the BT module */ diff --git a/arch/arm/boot/dts/bcm2838-rpi-4-b.dts b/arch/arm/boot/dts/bcm2838-rpi-4-b.dts index c851ba108543ab..7170a97bd3e4f0 100644 --- a/arch/arm/boot/dts/bcm2838-rpi-4-b.dts +++ b/arch/arm/boot/dts/bcm2838-rpi-4-b.dts @@ -5,7 +5,7 @@ #include "bcm2838-rpi.dtsi" / { - compatible = "raspberrypi,4-model-b", "brcm,bcm2838"; + compatible = "raspberrypi,4-model-b", "brcm,bcm2711"; model = "Raspberry Pi 4 Model B"; chosen { @@ -13,7 +13,7 @@ stdout-path = "serial1:115200n8"; }; - memory { + memory@0 { reg = <0 0 0x40000000>; }; diff --git a/arch/arm/boot/dts/bcm2838.dtsi b/arch/arm/boot/dts/bcm2838.dtsi index 1d321ad6640a66..c8a2c3e6ed6960 100644 --- a/arch/arm/boot/dts/bcm2838.dtsi +++ b/arch/arm/boot/dts/bcm2838.dtsi @@ -210,7 +210,7 @@ compatible = "brcm,bcm2711-emmc2"; status = "okay"; interrupts = ; - clocks = <&clocks BCM2838_CLOCK_EMMC2>; + clocks = <&clocks BCM2711_CLOCK_EMMC2>; reg = <0x7e340000 0x100>; }; @@ -440,7 +440,7 @@ }; &clocks { - compatible = "brcm,bcm2838-cprman"; + compatible = "brcm,bcm2711-cprman"; }; &cpu_thermal { @@ -456,7 +456,7 @@ }; &gpio { - compatible = "brcm,bcm2838-gpio", "brcm,bcm2835-gpio"; + compatible = "brcm,bcm2711-gpio", "brcm,bcm2835-gpio"; gpclk0_gpio49: gpclk0_gpio49 { brcm,pins = <49>; diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi index 914c4c14d714e4..fa18607874a947 100644 --- a/arch/arm/boot/dts/bcm283x.dtsi +++ b/arch/arm/boot/dts/bcm283x.dtsi @@ -403,6 +403,8 @@ reg = <0x7e204000 0x200>; interrupts = <2 22>; clocks = <&clocks BCM2835_CLOCK_VPU>; + dmas = <&dma 6>, <&dma 7>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; diff --git a/arch/arm/mach-bcm/board_bcm2835.c b/arch/arm/mach-bcm/board_bcm2835.c index 3784ce541113cc..d52391309de224 100644 --- a/arch/arm/mach-bcm/board_bcm2835.c +++ b/arch/arm/mach-bcm/board_bcm2835.c @@ -118,7 +118,7 @@ static const char * const bcm2835_compat[] = { #ifdef CONFIG_ARCH_MULTI_V7 "brcm,bcm2836", "brcm,bcm2837", - "brcm,bcm2838", + "brcm,bcm2711", #endif NULL }; diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index a885c2faa7b0b4..0db72aba7ec5c5 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -40,7 +40,7 @@ #include #include #include -#include +#include #include #include #include @@ -303,6 +303,10 @@ #define VCMSG_ID_CORE_CLOCK 4 +#define SOC_BCM2835 BIT(0) +#define SOC_BCM2711 BIT(1) +#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711) + /* * Names of clocks used within the driver that need to be replaced * with an external parent's name. This array is in the order that @@ -335,6 +339,10 @@ struct bcm2835_cprman { struct clk_hw_onecell_data onecell; }; +struct cprman_plat_data { + unsigned int soc; +}; + static inline void cprman_write(struct bcm2835_cprman *cprman, u32 reg, u32 val) { writel(CM_PASSWORD | val, cprman->regs + reg); @@ -1530,22 +1538,28 @@ typedef struct clk_hw *(*bcm2835_clk_register)(struct bcm2835_cprman *cprman, const void *data); struct bcm2835_clk_desc { bcm2835_clk_register clk_register; + unsigned int supported; const void *data; }; /* assignment helper macros for different clock types */ -#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \ - .data = __VA_ARGS__ } -#define REGISTER_PLL(...) _REGISTER(&bcm2835_register_pll, \ +#define _REGISTER(f, s, ...) { .clk_register = (bcm2835_clk_register)f, \ + .supported = s, \ + .data = __VA_ARGS__ } +#define REGISTER_PLL(s, ...) _REGISTER(&bcm2835_register_pll, \ + s, \ &(struct bcm2835_pll_data) \ {__VA_ARGS__}) -#define REGISTER_PLL_DIV(...) _REGISTER(&bcm2835_register_pll_divider, \ - &(struct bcm2835_pll_divider_data) \ - {__VA_ARGS__}) -#define REGISTER_CLK(...) _REGISTER(&bcm2835_register_clock, \ +#define REGISTER_PLL_DIV(s, ...) _REGISTER(&bcm2835_register_pll_divider, \ + s, \ + &(struct bcm2835_pll_divider_data) \ + {__VA_ARGS__}) +#define REGISTER_CLK(s, ...) _REGISTER(&bcm2835_register_clock, \ + s, \ &(struct bcm2835_clock_data) \ {__VA_ARGS__}) -#define REGISTER_GATE(...) _REGISTER(&bcm2835_register_gate, \ +#define REGISTER_GATE(s, ...) _REGISTER(&bcm2835_register_gate, \ + s, \ &(struct bcm2835_gate_data) \ {__VA_ARGS__}) @@ -1559,7 +1573,8 @@ static const char *const bcm2835_clock_osc_parents[] = { "testdebug1" }; -#define REGISTER_OSC_CLK(...) REGISTER_CLK( \ +#define REGISTER_OSC_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents), \ .parents = bcm2835_clock_osc_parents, \ __VA_ARGS__) @@ -1576,7 +1591,8 @@ static const char *const bcm2835_clock_per_parents[] = { "pllh_aux", }; -#define REGISTER_PER_CLK(...) REGISTER_CLK( \ +#define REGISTER_PER_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents), \ .parents = bcm2835_clock_per_parents, \ __VA_ARGS__) @@ -1601,7 +1617,8 @@ static const char *const bcm2835_pcm_per_parents[] = { "-", }; -#define REGISTER_PCM_CLK(...) REGISTER_CLK( \ +#define REGISTER_PCM_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_pcm_per_parents), \ .parents = bcm2835_pcm_per_parents, \ __VA_ARGS__) @@ -1620,7 +1637,8 @@ static const char *const bcm2835_clock_vpu_parents[] = { "pllc_core2", }; -#define REGISTER_VPU_CLK(...) REGISTER_CLK( \ +#define REGISTER_VPU_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents), \ .parents = bcm2835_clock_vpu_parents, \ __VA_ARGS__) @@ -1656,12 +1674,14 @@ static const char *const bcm2835_clock_dsi1_parents[] = { "dsi1_byte_inv", }; -#define REGISTER_DSI0_CLK(...) REGISTER_CLK( \ +#define REGISTER_DSI0_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi0_parents), \ .parents = bcm2835_clock_dsi0_parents, \ __VA_ARGS__) -#define REGISTER_DSI1_CLK(...) REGISTER_CLK( \ +#define REGISTER_DSI1_CLK(s, ...) REGISTER_CLK( \ + s, \ .num_mux_parents = ARRAY_SIZE(bcm2835_clock_dsi1_parents), \ .parents = bcm2835_clock_dsi1_parents, \ __VA_ARGS__) @@ -1681,6 +1701,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * AUDIO domain is on. */ [BCM2835_PLLA] = REGISTER_PLL( + SOC_ALL, .name = "plla", .cm_ctrl_reg = CM_PLLA, .a2w_ctrl_reg = A2W_PLLA_CTRL, @@ -1695,6 +1716,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .max_rate = 2400000000u, .max_fb_rate = BCM2835_MAX_FB_RATE), [BCM2835_PLLA_CORE] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plla_core", .source_pll = "plla", .cm_reg = CM_PLLA, @@ -1704,6 +1726,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLA_PER] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plla_per", .source_pll = "plla", .cm_reg = CM_PLLA, @@ -1713,6 +1736,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLA_DSI0] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plla_dsi0", .source_pll = "plla", .cm_reg = CM_PLLA, @@ -1721,6 +1745,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .hold_mask = CM_PLLA_HOLDDSI0, .fixed_divider = 1), [BCM2835_PLLA_CCP2] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plla_ccp2", .source_pll = "plla", .cm_reg = CM_PLLA, @@ -1732,6 +1757,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* PLLB is used for the ARM's clock. */ [BCM2835_PLLB] = REGISTER_PLL( + SOC_ALL, .name = "pllb", .cm_ctrl_reg = CM_PLLB, .a2w_ctrl_reg = A2W_PLLB_CTRL, @@ -1746,6 +1772,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .max_rate = 3000000000u, .max_fb_rate = BCM2835_MAX_FB_RATE), [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV( + SOC_ALL, .name = "pllb_arm", .source_pll = "pllb", .cm_reg = CM_PLLB, @@ -1762,6 +1789,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * AUDIO domain is on. */ [BCM2835_PLLC] = REGISTER_PLL( + SOC_ALL, .name = "pllc", .cm_ctrl_reg = CM_PLLC, .a2w_ctrl_reg = A2W_PLLC_CTRL, @@ -1776,6 +1804,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .max_rate = 3000000000u, .max_fb_rate = BCM2835_MAX_FB_RATE), [BCM2835_PLLC_CORE0] = REGISTER_PLL_DIV( + SOC_ALL, .name = "pllc_core0", .source_pll = "pllc", .cm_reg = CM_PLLC, @@ -1785,6 +1814,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLC_CORE1] = REGISTER_PLL_DIV( + SOC_ALL, .name = "pllc_core1", .source_pll = "pllc", .cm_reg = CM_PLLC, @@ -1794,6 +1824,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLC_CORE2] = REGISTER_PLL_DIV( + SOC_ALL, .name = "pllc_core2", .source_pll = "pllc", .cm_reg = CM_PLLC, @@ -1803,6 +1834,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLC_PER] = REGISTER_PLL_DIV( + SOC_ALL, .name = "pllc_per", .source_pll = "pllc", .cm_reg = CM_PLLC, @@ -1819,6 +1851,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * AUDIO domain is on. */ [BCM2835_PLLD] = REGISTER_PLL( + SOC_ALL, .name = "plld", .cm_ctrl_reg = CM_PLLD, .a2w_ctrl_reg = A2W_PLLD_CTRL, @@ -1833,6 +1866,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .max_rate = 2400000000u, .max_fb_rate = BCM2835_MAX_FB_RATE), [BCM2835_PLLD_CORE] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plld_core", .source_pll = "plld", .cm_reg = CM_PLLD, @@ -1842,6 +1876,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLD_PER] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plld_per", .source_pll = "plld", .cm_reg = CM_PLLD, @@ -1851,6 +1886,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLD_DSI0] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plld_dsi0", .source_pll = "plld", .cm_reg = CM_PLLD, @@ -1859,6 +1895,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .hold_mask = CM_PLLD_HOLDDSI0, .fixed_divider = 1), [BCM2835_PLLD_DSI1] = REGISTER_PLL_DIV( + SOC_ALL, .name = "plld_dsi1", .source_pll = "plld", .cm_reg = CM_PLLD, @@ -1874,6 +1911,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * It is in the HDMI power domain. */ [BCM2835_PLLH] = REGISTER_PLL( + SOC_BCM2835, "pllh", .cm_ctrl_reg = CM_PLLH, .a2w_ctrl_reg = A2W_PLLH_CTRL, @@ -1888,6 +1926,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .max_rate = 3000000000u, .max_fb_rate = BCM2835_MAX_FB_RATE), [BCM2835_PLLH_RCAL] = REGISTER_PLL_DIV( + SOC_BCM2835, .name = "pllh_rcal", .source_pll = "pllh", .cm_reg = CM_PLLH, @@ -1897,6 +1936,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 10, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLH_AUX] = REGISTER_PLL_DIV( + SOC_BCM2835, .name = "pllh_aux", .source_pll = "pllh", .cm_reg = CM_PLLH, @@ -1906,6 +1946,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .fixed_divider = 1, .flags = CLK_SET_RATE_PARENT), [BCM2835_PLLH_PIX] = REGISTER_PLL_DIV( + SOC_BCM2835, .name = "pllh_pix", .source_pll = "pllh", .cm_reg = CM_PLLH, @@ -1921,6 +1962,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* One Time Programmable Memory clock. Maximum 10Mhz. */ [BCM2835_CLOCK_OTP] = REGISTER_OSC_CLK( + SOC_ALL, .name = "otp", .ctl_reg = CM_OTPCTL, .div_reg = CM_OTPDIV, @@ -1932,6 +1974,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * bythe watchdog timer and the camera pulse generator. */ [BCM2835_CLOCK_TIMER] = REGISTER_OSC_CLK( + SOC_ALL, .name = "timer", .ctl_reg = CM_TIMERCTL, .div_reg = CM_TIMERDIV, @@ -1942,12 +1985,14 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * Generally run at 2Mhz, max 5Mhz. */ [BCM2835_CLOCK_TSENS] = REGISTER_OSC_CLK( + SOC_ALL, .name = "tsens", .ctl_reg = CM_TSENSCTL, .div_reg = CM_TSENSDIV, .int_bits = 5, .frac_bits = 0), [BCM2835_CLOCK_TEC] = REGISTER_OSC_CLK( + SOC_ALL, .name = "tec", .ctl_reg = CM_TECCTL, .div_reg = CM_TECDIV, @@ -1956,6 +2001,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* clocks with vpu parent mux */ [BCM2835_CLOCK_H264] = REGISTER_VPU_CLK( + SOC_ALL, .name = "h264", .ctl_reg = CM_H264CTL, .div_reg = CM_H264DIV, @@ -1963,6 +2009,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 1), [BCM2835_CLOCK_ISP] = REGISTER_VPU_CLK( + SOC_ALL, .name = "isp", .ctl_reg = CM_ISPCTL, .div_reg = CM_ISPDIV, @@ -1975,6 +2022,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * in the SDRAM controller can't be used. */ [BCM2835_CLOCK_SDRAM] = REGISTER_VPU_CLK( + SOC_ALL, .name = "sdram", .ctl_reg = CM_SDCCTL, .div_reg = CM_SDCDIV, @@ -1982,6 +2030,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 0, .tcnt_mux = 3), [BCM2835_CLOCK_V3D] = REGISTER_VPU_CLK( + SOC_ALL, .name = "v3d", .ctl_reg = CM_V3DCTL, .div_reg = CM_V3DDIV, @@ -1995,6 +2044,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * in various hardware documentation. */ [BCM2835_CLOCK_VPU] = REGISTER_VPU_CLK( + SOC_ALL, .name = "vpu", .ctl_reg = CM_VPUCTL, .div_reg = CM_VPUDIV, @@ -2006,6 +2056,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* clocks with per parent mux */ [BCM2835_CLOCK_AVEO] = REGISTER_PER_CLK( + SOC_ALL, .name = "aveo", .ctl_reg = CM_AVEOCTL, .div_reg = CM_AVEODIV, @@ -2013,6 +2064,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 0, .tcnt_mux = 38), [BCM2835_CLOCK_CAM0] = REGISTER_PER_CLK( + SOC_ALL, .name = "cam0", .ctl_reg = CM_CAM0CTL, .div_reg = CM_CAM0DIV, @@ -2020,6 +2072,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 14), [BCM2835_CLOCK_CAM1] = REGISTER_PER_CLK( + SOC_ALL, .name = "cam1", .ctl_reg = CM_CAM1CTL, .div_reg = CM_CAM1DIV, @@ -2027,12 +2080,14 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 15), [BCM2835_CLOCK_DFT] = REGISTER_PER_CLK( + SOC_ALL, .name = "dft", .ctl_reg = CM_DFTCTL, .div_reg = CM_DFTDIV, .int_bits = 5, .frac_bits = 0), [BCM2835_CLOCK_DPI] = REGISTER_PER_CLK( + SOC_ALL, .name = "dpi", .ctl_reg = CM_DPICTL, .div_reg = CM_DPIDIV, @@ -2042,6 +2097,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* Arasan EMMC clock */ [BCM2835_CLOCK_EMMC] = REGISTER_PER_CLK( + SOC_ALL, .name = "emmc", .ctl_reg = CM_EMMCCTL, .div_reg = CM_EMMCDIV, @@ -2049,8 +2105,9 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 39), - /* EMMC2 clock (only available for BCM2838) */ - [BCM2838_CLOCK_EMMC2] = REGISTER_PER_CLK( + /* EMMC2 clock (only available for BCM2711) */ + [BCM2711_CLOCK_EMMC2] = REGISTER_PER_CLK( + SOC_BCM2711, .name = "emmc2", .ctl_reg = CM_EMMC2CTL, .div_reg = CM_EMMC2DIV, @@ -2060,6 +2117,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* General purpose (GPIO) clocks */ [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( + SOC_ALL, .name = "gp0", .ctl_reg = CM_GP0CTL, .div_reg = CM_GP0DIV, @@ -2068,6 +2126,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .is_mash_clock = true, .tcnt_mux = 20), [BCM2835_CLOCK_GP1] = REGISTER_PER_CLK( + SOC_ALL, .name = "gp1", .ctl_reg = CM_GP1CTL, .div_reg = CM_GP1DIV, @@ -2077,6 +2136,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .is_mash_clock = true, .tcnt_mux = 21), [BCM2835_CLOCK_GP2] = REGISTER_PER_CLK( + SOC_ALL, .name = "gp2", .ctl_reg = CM_GP2CTL, .div_reg = CM_GP2DIV, @@ -2086,6 +2146,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* HDMI state machine */ [BCM2835_CLOCK_HSM] = REGISTER_PER_CLK( + SOC_ALL, .name = "hsm", .ctl_reg = CM_HSMCTL, .div_reg = CM_HSMDIV, @@ -2093,6 +2154,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 22), [BCM2835_CLOCK_PCM] = REGISTER_PCM_CLK( + SOC_ALL, .name = "pcm", .ctl_reg = CM_PCMCTL, .div_reg = CM_PCMDIV, @@ -2102,6 +2164,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .low_jitter = true, .tcnt_mux = 23), [BCM2835_CLOCK_PWM] = REGISTER_PER_CLK( + SOC_ALL, .name = "pwm", .ctl_reg = CM_PWMCTL, .div_reg = CM_PWMDIV, @@ -2110,6 +2173,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .is_mash_clock = true, .tcnt_mux = 24), [BCM2835_CLOCK_SLIM] = REGISTER_PER_CLK( + SOC_ALL, .name = "slim", .ctl_reg = CM_SLIMCTL, .div_reg = CM_SLIMDIV, @@ -2118,6 +2182,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .is_mash_clock = true, .tcnt_mux = 25), [BCM2835_CLOCK_SMI] = REGISTER_PER_CLK( + SOC_ALL, .name = "smi", .ctl_reg = CM_SMICTL, .div_reg = CM_SMIDIV, @@ -2125,6 +2190,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 27), [BCM2835_CLOCK_UART] = REGISTER_PER_CLK( + SOC_ALL, .name = "uart", .ctl_reg = CM_UARTCTL, .div_reg = CM_UARTDIV, @@ -2134,6 +2200,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* TV encoder clock. Only operating frequency is 108Mhz. */ [BCM2835_CLOCK_VEC] = REGISTER_PER_CLK( + SOC_ALL, .name = "vec", .ctl_reg = CM_VECCTL, .div_reg = CM_VECDIV, @@ -2148,6 +2215,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { /* dsi clocks */ [BCM2835_CLOCK_DSI0E] = REGISTER_PER_CLK( + SOC_ALL, .name = "dsi0e", .ctl_reg = CM_DSI0ECTL, .div_reg = CM_DSI0EDIV, @@ -2155,6 +2223,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 18), [BCM2835_CLOCK_DSI1E] = REGISTER_PER_CLK( + SOC_ALL, .name = "dsi1e", .ctl_reg = CM_DSI1ECTL, .div_reg = CM_DSI1EDIV, @@ -2162,6 +2231,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 19), [BCM2835_CLOCK_DSI0P] = REGISTER_DSI0_CLK( + SOC_ALL, .name = "dsi0p", .ctl_reg = CM_DSI0PCTL, .div_reg = CM_DSI0PDIV, @@ -2169,6 +2239,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 0, .tcnt_mux = 12), [BCM2835_CLOCK_DSI1P] = REGISTER_DSI1_CLK( + SOC_ALL, .name = "dsi1p", .ctl_reg = CM_DSI1PCTL, .div_reg = CM_DSI1PDIV, @@ -2185,6 +2256,7 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { * non-stop vpu clock. */ [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE( + SOC_ALL, .name = "peri_image", .parent = "vpu", .ctl_reg = CM_PERIICTL), @@ -2232,11 +2304,16 @@ static int bcm2835_clk_probe(struct platform_device *pdev) struct resource *res; const struct bcm2835_clk_desc *desc; const size_t asize = ARRAY_SIZE(clk_desc_array); + const struct cprman_plat_data *pdata; struct device_node *fw_node; size_t i; u32 clk_id; int ret; + pdata = of_device_get_match_data(&pdev->dev); + if (!pdata) + return -ENODEV; + cprman = devm_kzalloc(dev, struct_size(cprman, onecell.hws, asize), GFP_KERNEL); @@ -2287,11 +2364,9 @@ static int bcm2835_clk_probe(struct platform_device *pdev) for (i = 0; i < asize; i++) { desc = &clk_desc_array[i]; - if (desc->clk_register && desc->data) { - if ((i != BCM2838_CLOCK_EMMC2) || - of_device_is_compatible(fw_node, "brcm,bcm2838-cprman")) { - hws[i] = desc->clk_register(cprman, desc->data); - } + if (desc->clk_register && desc->data && + (desc->supported & pdata->soc)) { + hws[i] = desc->clk_register(cprman, desc->data); } } @@ -2310,9 +2385,17 @@ static int bcm2835_clk_probe(struct platform_device *pdev) return 0; } +static const struct cprman_plat_data cprman_bcm2835_plat_data = { + .soc = SOC_BCM2835, +}; + +static const struct cprman_plat_data cprman_bcm2711_plat_data = { + .soc = SOC_BCM2711, +}; + static const struct of_device_id bcm2835_clk_of_match[] = { - { .compatible = "brcm,bcm2835-cprman", }, - { .compatible = "brcm,bcm2838-cprman", }, + { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data }, + { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data }, {} }; MODULE_DEVICE_TABLE(of, bcm2835_clk_of_match); diff --git a/drivers/pinctrl/bcm/pinctrl-bcm2835.c b/drivers/pinctrl/bcm/pinctrl-bcm2835.c index 0a61292924ec29..9f91e453b30bc3 100644 --- a/drivers/pinctrl/bcm/pinctrl-bcm2835.c +++ b/drivers/pinctrl/bcm/pinctrl-bcm2835.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO) * @@ -6,16 +7,6 @@ * This driver is inspired by: * pinctrl-nomadik.c, please see original file for copyright information * pinctrl-tegra.c, please see original file for copyright information - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ #include @@ -66,22 +57,23 @@ #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */ #define GPPUD 0x94 /* Pin Pull-up/down Enable */ #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */ - -/* 2711 has a different mechanism for pin pull-up/down/enable */ -#define GPPUPPDN0 0xe4 /* Pin pull-up/down for pins 15:0 */ -#define GPPUPPDN1 0xe8 /* Pin pull-up/down for pins 31:16 */ -#define GPPUPPDN2 0xec /* Pin pull-up/down for pins 47:32 */ -#define GPPUPPDN3 0xf0 /* Pin pull-up/down for pins 57:48 */ +#define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */ #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4)) #define FSEL_SHIFT(p) (((p) % 10) * 3) #define GPIO_REG_OFFSET(p) ((p) / 32) #define GPIO_REG_SHIFT(p) ((p) % 32) -enum bcm2835_pinconf_param { - /* argument: bcm2835_pinconf_pull */ - BCM2835_PINCONF_PARAM_PULL = (PIN_CONFIG_END + 1), -}; +#define PUD_2711_MASK 0x3 +#define PUD_2711_REG_OFFSET(p) ((p) / 16) +#define PUD_2711_REG_SHIFT(p) (((p) % 16) * 2) + +/* argument: bcm2835_pinconf_pull */ +#define BCM2835_PINCONF_PARAM_PULL (PIN_CONFIG_END + 1) + +#define BCM2711_PULL_NONE 0x0 +#define BCM2711_PULL_UP 0x1 +#define BCM2711_PULL_DOWN 0x2 struct bcm2835_pinctrl { struct device *dev; @@ -359,6 +351,7 @@ static const struct gpio_chip bcm2835_gpio_chip = { .get = bcm2835_gpio_get, .set = bcm2835_gpio_set, .base = 0, + .set_config = gpiochip_generic_config, .ngpio = BCM2835_NUM_GPIOS, .can_sleep = false, }; @@ -923,45 +916,21 @@ static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc, unsigned int pin, unsigned int arg) { u32 off, bit; - /* BCM2835, BCM2836 & BCM2837 return 'gpio' for this unused register */ - int is_2835 = bcm2835_gpio_rd(pc, GPPUPPDN3) == 0x6770696f; - if (is_2835) { - off = GPIO_REG_OFFSET(pin); - bit = GPIO_REG_SHIFT(pin); - /* - * BCM2835 datasheet say to wait 150 cycles, but not of what. - * But the VideoCore firmware delay for this operation - * based nearly on the same amount of VPU cycles and this clock - * runs at 250 MHz. - */ - bcm2835_gpio_wr(pc, GPPUD, arg & 3); - udelay(1); - bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); - udelay(1); - bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); - } else { - u32 reg; - int lsb; - - off = (pin >> 4); - if (off > 3) - return; - lsb = (pin & 0xf) << 1; - - /* The up/down semantics are reversed compared to BCM2835. - * Instead of updating all the device tree files, translate the - * values here. - */ - if (arg == 2) - arg = 1; - else if (arg == 1) - arg = 2; - reg = bcm2835_gpio_rd(pc, GPPUPPDN0 + (off *4)); - reg &= ~(0x3 << lsb); - reg |= (arg & 3) << lsb; - bcm2835_gpio_wr(pc, GPPUPPDN0 + (off * 4), reg); - } + off = GPIO_REG_OFFSET(pin); + bit = GPIO_REG_SHIFT(pin); + + bcm2835_gpio_wr(pc, GPPUD, arg & 3); + /* + * BCM2835 datasheet say to wait 150 cycles, but not of what. + * But the VideoCore firmware delay for this operation + * based nearly on the same amount of VPU cycles and this clock + * runs at 250 MHz. + */ + udelay(1); + bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit)); + udelay(1); + bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0); } static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, @@ -1001,7 +970,7 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, break; default: - return -EINVAL; + return -ENOTSUPP; } /* switch param type */ } /* for each config */ @@ -1010,10 +979,82 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev, } static const struct pinconf_ops bcm2835_pinconf_ops = { + .is_generic = true, .pin_config_get = bcm2835_pinconf_get, .pin_config_set = bcm2835_pinconf_set, }; +static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc, + unsigned int pin, unsigned int arg) +{ + u32 shifter; + u32 value; + u32 off; + + off = PUD_2711_REG_OFFSET(pin); + shifter = PUD_2711_REG_SHIFT(pin); + + value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4)); + value &= ~(PUD_2711_MASK << shifter); + value |= (arg << shifter); + bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value); +} + +static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev); + u32 param, arg; + int i; + + for (i = 0; i < num_configs; i++) { + param = pinconf_to_config_param(configs[i]); + arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + /* convert legacy brcm,pull */ + case BCM2835_PINCONF_PARAM_PULL: + if (arg == BCM2835_PUD_UP) + arg = BCM2711_PULL_UP; + else if (arg == BCM2835_PUD_DOWN) + arg = BCM2711_PULL_DOWN; + else + arg = BCM2711_PULL_NONE; + + bcm2711_pull_config_set(pc, pin, arg); + break; + + /* Set pull generic bindings */ + case PIN_CONFIG_BIAS_DISABLE: + bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN); + break; + case PIN_CONFIG_BIAS_PULL_UP: + bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP); + break; + + /* Set output-high or output-low */ + case PIN_CONFIG_OUTPUT: + bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin); + break; + + default: + return -ENOTSUPP; + } + } /* for each config */ + + return 0; +} + +static const struct pinconf_ops bcm2711_pinconf_ops = { + .is_generic = true, + .pin_config_get = bcm2835_pinconf_get, + .pin_config_set = bcm2711_pinconf_set, +}; + static struct pinctrl_desc bcm2835_pinctrl_desc = { .name = MODULE_NAME, .pins = bcm2835_gpio_pins, @@ -1029,6 +1070,18 @@ static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = { .npins = BCM2835_NUM_GPIOS, }; +static const struct of_device_id bcm2835_pinctrl_match[] = { + { + .compatible = "brcm,bcm2835-gpio", + .data = &bcm2835_pinconf_ops, + }, + { + .compatible = "brcm,bcm2711-gpio", + .data = &bcm2711_pinconf_ops, + }, + {} +}; + static int bcm2835_pinctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1036,6 +1089,8 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) struct bcm2835_pinctrl *pc; struct resource iomem; int err, i; + const struct of_device_id *match; + BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS); BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS); @@ -1112,6 +1167,12 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) bcm2835_gpio_irq_handler); } + match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node); + if (match) { + bcm2835_pinctrl_desc.confops = + (const struct pinconf_ops *)match->data; + } + pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc); if (IS_ERR(pc->pctl_dev)) { gpiochip_remove(&pc->gpio_chip); @@ -1126,11 +1187,6 @@ static int bcm2835_pinctrl_probe(struct platform_device *pdev) return 0; } -static const struct of_device_id bcm2835_pinctrl_match[] = { - { .compatible = "brcm,bcm2835-gpio" }, - {} -}; - static struct platform_driver bcm2835_pinctrl_driver = { .probe = bcm2835_pinctrl_probe, .driver = { diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h index 077796e8f24b19..f2ceddd8331fd5 100644 --- a/include/dt-bindings/clock/bcm2835.h +++ b/include/dt-bindings/clock/bcm2835.h @@ -67,4 +67,4 @@ #define BCM2835_CLOCK_DSI0P 49 #define BCM2835_CLOCK_DSI1P 50 -#define BCM2838_CLOCK_EMMC2 51 +#define BCM2711_CLOCK_EMMC2 51 diff --git a/include/dt-bindings/pinctrl/bcm2835.h b/include/dt-bindings/pinctrl/bcm2835.h index e4e4fdf5d38fbe..b5b2654a0e4dc5 100644 --- a/include/dt-bindings/pinctrl/bcm2835.h +++ b/include/dt-bindings/pinctrl/bcm2835.h @@ -1,14 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ /* * Header providing constants for bcm2835 pinctrl bindings. * * Copyright (C) 2015 Stefan Wahren - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html */ #ifndef __DT_BINDINGS_PINCTRL_BCM2835_H__