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vc4/hvs: Support fixed alpha correctly on 2712D0
2712D0 removed alpha_mode from control word 2 for choosing fixed alpha and replaced it with the previously reserved value of 3 in alpha_mask. Handle this to fix corrupt desktop when using X on 2712D0 Signed-off-by: Dom Cobley <[email protected]>
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+18
-1
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2 files changed

+18
-1
lines changed

drivers/gpu/drm/vc4/vc4_plane.c

Lines changed: 15 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1079,6 +1079,20 @@ static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state)
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}
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}
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1082+
static u32 vc4_hvs6_get_alpha_mask_mode(struct drm_plane_state *state)
1083+
{
1084+
struct drm_device *dev = state->state->dev;
1085+
struct vc4_dev *vc4 = to_vc4_dev(dev);
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1087+
WARN_ON_ONCE(vc4->gen != VC4_GEN_6);
1088+
1089+
if (vc4->step_d0 && (!state->fb->format->has_alpha ||
1090+
state->pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE))
1091+
return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_FIXED,
1092+
SCALER6_CTL0_ALPHA_MASK);
1093+
return VC4_SET_FIELD(SCALER6_CTL0_ALPHA_MASK_NONE, SCALER6_CTL0_ALPHA_MASK);
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}
1095+
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/* Writes out a full display list for an active plane to the plane's
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* private dlist state.
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*/
@@ -1822,7 +1836,7 @@ static int vc6_plane_mode_set(struct drm_plane *plane,
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vc4_dlist_write(vc4_state,
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SCALER6_CTL0_VALID |
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VC4_SET_FIELD(tiling, SCALER6_CTL0_ADDR_MODE) |
1825-
VC4_SET_FIELD(0, SCALER6_CTL0_ALPHA_MASK) |
1839+
vc4_hvs6_get_alpha_mask_mode(state) |
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(vc4_state->is_unity ? SCALER6_CTL0_UNITY : 0) |
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VC4_SET_FIELD(format->pixel_order_hvs5, SCALER6_CTL0_ORDERRGBA) |
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VC4_SET_FIELD(scl1, SCALER6_CTL0_SCL1_MODE) |

drivers/gpu/drm/vc4/vc4_regs.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1408,6 +1408,9 @@ enum hvs_pixel_format {
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#define SCALER6_CTL0_ADDR_MODE_UIF 4
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#define SCALER6_CTL0_ALPHA_MASK_MASK VC4_MASK(19, 18)
1411+
#define SCALER6_CTL0_ALPHA_MASK_NONE 0
1412+
#define SCALER6_CTL0_ALPHA_MASK_FIXED 3
1413+
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#define SCALER6_CTL0_UNITY BIT(15)
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#define SCALER6_CTL0_ORDERRGBA_MASK VC4_MASK(14, 13)
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#define SCALER6_CTL0_SCL1_MODE_MASK VC4_MASK(10, 8)

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