From 3dff0e64418dd399ca40c07efc5d3721ec696477 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 2 Nov 2023 22:32:18 -0700 Subject: [PATCH 1/2] [Mips] In LowerShift*Parts, xor with bits-1 instead of -1. If we start with an i128 shift, the initial shift amount would usually have zeros in bit 8 and above. xoring the shift amount with -1 will set those upper bits to 1. If DAGCombiner is able to prove those bits are now 1, then the shift that uses the xor will be replaced with undef. Which we don't want. Reduce the xor constant to VT.bits-1 where VT is half the size of the larger shift type. This avoids toggling the upper bits. The hardware shift instruction only uses the lower bits of the shift amount. I assume the code used NOT because the hardware doesn't use the upper bits, but that isn't compatible with the LLVM poison semantics. Fixes #71142. --- llvm/lib/Target/Mips/MipsISelLowering.cpp | 14 ++++++------ llvm/test/CodeGen/Mips/llvm-ir/ashr.ll | 24 ++++++++++----------- llvm/test/CodeGen/Mips/llvm-ir/lshr.ll | 26 +++++++++++------------ llvm/test/CodeGen/Mips/llvm-ir/shl.ll | 26 +++++++++++------------ 4 files changed, 46 insertions(+), 44 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 061d035b7e246..dbc790c5663fd 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -2593,12 +2593,13 @@ SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, SDValue Shamt = Op.getOperand(2); // if shamt < (VT.bits): // lo = (shl lo, shamt) - // hi = (or (shl hi, shamt) (srl (srl lo, 1), ~shamt)) + // hi = (or (shl hi, shamt) (srl (srl lo, 1), (VT.bits-1) ^ shamt)) // else: // lo = 0 // hi = (shl lo, shamt[4:0]) - SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, - DAG.getConstant(-1, DL, MVT::i32)); + SDValue Not = + DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, + DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32)); SDValue ShiftRight1Lo = DAG.getNode(ISD::SRL, DL, VT, Lo, DAG.getConstant(1, DL, VT)); SDValue ShiftRightLo = DAG.getNode(ISD::SRL, DL, VT, ShiftRight1Lo, Not); @@ -2623,7 +2624,7 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; // if shamt < (VT.bits): - // lo = (or (shl (shl hi, 1), ~shamt) (srl lo, shamt)) + // lo = (or (shl (shl hi, 1), (VT.bits-1) ^ shamt) (srl lo, shamt)) // if isSRA: // hi = (sra hi, shamt) // else: @@ -2635,8 +2636,9 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, // else: // lo = (srl hi, shamt[4:0]) // hi = 0 - SDValue Not = DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, - DAG.getConstant(-1, DL, MVT::i32)); + SDValue Not = + DAG.getNode(ISD::XOR, DL, MVT::i32, Shamt, + DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32)); SDValue ShiftLeft1Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(1, DL, VT)); SDValue ShiftLeftHi = DAG.getNode(ISD::SHL, DL, VT, ShiftLeft1Hi, Not); diff --git a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll index 47d18b9b5c533..453ca0d6bab3b 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -280,7 +280,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { ; MIPS-NEXT: srav $3, $4, $7 ; MIPS-NEXT: # %bb.1: # %entry ; MIPS-NEXT: srlv $1, $5, $7 -; MIPS-NEXT: not $2, $7 +; MIPS-NEXT: xori $2, $7, 31 ; MIPS-NEXT: sll $4, $4, 1 ; MIPS-NEXT: sllv $2, $4, $2 ; MIPS-NEXT: or $1, $2, $1 @@ -294,7 +294,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { ; MIPS32-LABEL: ashr_i64: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: srlv $1, $5, $7 -; MIPS32-NEXT: not $2, $7 +; MIPS32-NEXT: xori $2, $7, 31 ; MIPS32-NEXT: sll $3, $4, 1 ; MIPS32-NEXT: sllv $2, $3, $2 ; MIPS32-NEXT: or $3, $2, $1 @@ -308,7 +308,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { ; 32R2-LABEL: ashr_i64: ; 32R2: # %bb.0: # %entry ; 32R2-NEXT: srlv $1, $5, $7 -; 32R2-NEXT: not $2, $7 +; 32R2-NEXT: xori $2, $7, 31 ; 32R2-NEXT: sll $3, $4, 1 ; 32R2-NEXT: sllv $2, $3, $2 ; 32R2-NEXT: or $3, $2, $1 @@ -328,7 +328,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { ; 32R6-NEXT: selnez $6, $6, $3 ; 32R6-NEXT: or $2, $6, $2 ; 32R6-NEXT: srlv $5, $5, $7 -; 32R6-NEXT: not $6, $7 +; 32R6-NEXT: xori $6, $7, 31 ; 32R6-NEXT: sll $4, $4, 1 ; 32R6-NEXT: sllv $4, $4, $6 ; 32R6-NEXT: or $4, $4, $5 @@ -360,9 +360,9 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { ; MMR3-LABEL: ashr_i64: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: srlv $2, $5, $7 -; MMR3-NEXT: not16 $3, $7 -; MMR3-NEXT: sll16 $5, $4, 1 -; MMR3-NEXT: sllv $3, $5, $3 +; MMR3-NEXT: xori $1, $7, 31 +; MMR3-NEXT: sll16 $3, $4, 1 +; MMR3-NEXT: sllv $3, $3, $1 ; MMR3-NEXT: or16 $3, $2 ; MMR3-NEXT: srav $2, $4, $7 ; MMR3-NEXT: andi16 $5, $7, 32 @@ -380,7 +380,7 @@ define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { ; MMR6-NEXT: selnez $6, $6, $3 ; MMR6-NEXT: or $2, $6, $2 ; MMR6-NEXT: srlv $5, $5, $7 -; MMR6-NEXT: not16 $6, $7 +; MMR6-NEXT: xori $6, $7, 31 ; MMR6-NEXT: sll16 $4, $4, 1 ; MMR6-NEXT: sllv $4, $4, $6 ; MMR6-NEXT: or $4, $4, $5 @@ -609,7 +609,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { ; MIPS3-NEXT: # %bb.1: # %entry ; MIPS3-NEXT: dsrlv $1, $5, $7 ; MIPS3-NEXT: dsll $4, $4, 1 -; MIPS3-NEXT: not $2, $2 +; MIPS3-NEXT: xori $2, $2, 63 ; MIPS3-NEXT: dsllv $2, $4, $2 ; MIPS3-NEXT: or $1, $2, $1 ; MIPS3-NEXT: move $2, $3 @@ -624,7 +624,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { ; MIPS64-NEXT: dsrlv $1, $5, $7 ; MIPS64-NEXT: dsll $2, $4, 1 ; MIPS64-NEXT: sll $5, $7, 0 -; MIPS64-NEXT: not $3, $5 +; MIPS64-NEXT: xori $3, $5, 63 ; MIPS64-NEXT: dsllv $2, $2, $3 ; MIPS64-NEXT: or $3, $2, $1 ; MIPS64-NEXT: dsrav $2, $4, $7 @@ -639,7 +639,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { ; MIPS64R2-NEXT: dsrlv $1, $5, $7 ; MIPS64R2-NEXT: dsll $2, $4, 1 ; MIPS64R2-NEXT: sll $5, $7, 0 -; MIPS64R2-NEXT: not $3, $5 +; MIPS64R2-NEXT: xori $3, $5, 63 ; MIPS64R2-NEXT: dsllv $2, $2, $3 ; MIPS64R2-NEXT: or $3, $2, $1 ; MIPS64R2-NEXT: dsrav $2, $4, $7 @@ -661,7 +661,7 @@ define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { ; MIPS64R6-NEXT: or $2, $8, $2 ; MIPS64R6-NEXT: dsrlv $5, $5, $7 ; MIPS64R6-NEXT: dsll $4, $4, 1 -; MIPS64R6-NEXT: not $3, $3 +; MIPS64R6-NEXT: xori $3, $3, 63 ; MIPS64R6-NEXT: dsllv $3, $4, $3 ; MIPS64R6-NEXT: or $3, $3, $5 ; MIPS64R6-NEXT: seleqz $3, $3, $6 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll index c4e05117d28e1..ddbb1f217837a 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -283,7 +283,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { ; MIPS2-NEXT: addiu $2, $zero, 0 ; MIPS2-NEXT: # %bb.1: # %entry ; MIPS2-NEXT: srlv $1, $5, $7 -; MIPS2-NEXT: not $2, $7 +; MIPS2-NEXT: xori $2, $7, 31 ; MIPS2-NEXT: sll $3, $4, 1 ; MIPS2-NEXT: sllv $2, $3, $2 ; MIPS2-NEXT: or $3, $2, $1 @@ -296,7 +296,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { ; MIPS32-LABEL: lshr_i64: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: srlv $1, $5, $7 -; MIPS32-NEXT: not $2, $7 +; MIPS32-NEXT: xori $2, $7, 31 ; MIPS32-NEXT: sll $3, $4, 1 ; MIPS32-NEXT: sllv $2, $3, $2 ; MIPS32-NEXT: or $3, $2, $1 @@ -309,7 +309,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { ; MIPS32R2-LABEL: lshr_i64: ; MIPS32R2: # %bb.0: # %entry ; MIPS32R2-NEXT: srlv $1, $5, $7 -; MIPS32R2-NEXT: not $2, $7 +; MIPS32R2-NEXT: xori $2, $7, 31 ; MIPS32R2-NEXT: sll $3, $4, 1 ; MIPS32R2-NEXT: sllv $2, $3, $2 ; MIPS32R2-NEXT: or $3, $2, $1 @@ -322,7 +322,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { ; MIPS32R6-LABEL: lshr_i64: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: srlv $1, $5, $7 -; MIPS32R6-NEXT: not $2, $7 +; MIPS32R6-NEXT: xori $2, $7, 31 ; MIPS32R6-NEXT: sll $3, $4, 1 ; MIPS32R6-NEXT: sllv $2, $3, $2 ; MIPS32R6-NEXT: or $1, $2, $1 @@ -362,9 +362,9 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { ; MMR3-LABEL: lshr_i64: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: srlv $2, $5, $7 -; MMR3-NEXT: not16 $3, $7 -; MMR3-NEXT: sll16 $5, $4, 1 -; MMR3-NEXT: sllv $3, $5, $3 +; MMR3-NEXT: xori $1, $7, 31 +; MMR3-NEXT: sll16 $3, $4, 1 +; MMR3-NEXT: sllv $3, $3, $1 ; MMR3-NEXT: or16 $3, $2 ; MMR3-NEXT: srlv $2, $4, $7 ; MMR3-NEXT: andi16 $4, $7, 32 @@ -376,7 +376,7 @@ define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { ; MMR6-LABEL: lshr_i64: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: srlv $1, $5, $7 -; MMR6-NEXT: not16 $2, $7 +; MMR6-NEXT: xori $2, $7, 31 ; MMR6-NEXT: sll16 $3, $4, 1 ; MMR6-NEXT: sllv $2, $3, $2 ; MMR6-NEXT: or $1, $2, $1 @@ -606,7 +606,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { ; MIPS3-NEXT: # %bb.1: # %entry ; MIPS3-NEXT: dsrlv $1, $5, $7 ; MIPS3-NEXT: dsll $2, $4, 1 -; MIPS3-NEXT: not $3, $3 +; MIPS3-NEXT: xori $3, $3, 63 ; MIPS3-NEXT: dsllv $2, $2, $3 ; MIPS3-NEXT: or $3, $2, $1 ; MIPS3-NEXT: jr $ra @@ -620,7 +620,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { ; MIPS4-NEXT: dsrlv $1, $5, $7 ; MIPS4-NEXT: dsll $2, $4, 1 ; MIPS4-NEXT: sll $5, $7, 0 -; MIPS4-NEXT: not $3, $5 +; MIPS4-NEXT: xori $3, $5, 63 ; MIPS4-NEXT: dsllv $2, $2, $3 ; MIPS4-NEXT: or $3, $2, $1 ; MIPS4-NEXT: dsrlv $2, $4, $7 @@ -634,7 +634,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { ; MIPS64-NEXT: dsrlv $1, $5, $7 ; MIPS64-NEXT: dsll $2, $4, 1 ; MIPS64-NEXT: sll $5, $7, 0 -; MIPS64-NEXT: not $3, $5 +; MIPS64-NEXT: xori $3, $5, 63 ; MIPS64-NEXT: dsllv $2, $2, $3 ; MIPS64-NEXT: or $3, $2, $1 ; MIPS64-NEXT: dsrlv $2, $4, $7 @@ -648,7 +648,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { ; MIPS64R2-NEXT: dsrlv $1, $5, $7 ; MIPS64R2-NEXT: dsll $2, $4, 1 ; MIPS64R2-NEXT: sll $5, $7, 0 -; MIPS64R2-NEXT: not $3, $5 +; MIPS64R2-NEXT: xori $3, $5, 63 ; MIPS64R2-NEXT: dsllv $2, $2, $3 ; MIPS64R2-NEXT: or $3, $2, $1 ; MIPS64R2-NEXT: dsrlv $2, $4, $7 @@ -662,7 +662,7 @@ define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { ; MIPS64R6-NEXT: dsrlv $1, $5, $7 ; MIPS64R6-NEXT: dsll $2, $4, 1 ; MIPS64R6-NEXT: sll $3, $7, 0 -; MIPS64R6-NEXT: not $5, $3 +; MIPS64R6-NEXT: xori $5, $3, 63 ; MIPS64R6-NEXT: dsllv $2, $2, $5 ; MIPS64R6-NEXT: or $1, $2, $1 ; MIPS64R6-NEXT: andi $2, $3, 64 diff --git a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll index 77f9f0ed646ee..256da0b89e603 100644 --- a/llvm/test/CodeGen/Mips/llvm-ir/shl.ll +++ b/llvm/test/CodeGen/Mips/llvm-ir/shl.ll @@ -343,7 +343,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { ; MIPS2-NEXT: nop ; MIPS2-NEXT: $BB4_3: # %entry ; MIPS2-NEXT: sllv $1, $4, $7 -; MIPS2-NEXT: not $2, $7 +; MIPS2-NEXT: xori $2, $7, 31 ; MIPS2-NEXT: srl $3, $5, 1 ; MIPS2-NEXT: srlv $2, $3, $2 ; MIPS2-NEXT: or $2, $1, $2 @@ -356,7 +356,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { ; MIPS32-LABEL: shl_i64: ; MIPS32: # %bb.0: # %entry ; MIPS32-NEXT: sllv $1, $4, $7 -; MIPS32-NEXT: not $2, $7 +; MIPS32-NEXT: xori $2, $7, 31 ; MIPS32-NEXT: srl $3, $5, 1 ; MIPS32-NEXT: srlv $2, $3, $2 ; MIPS32-NEXT: or $2, $1, $2 @@ -369,7 +369,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { ; MIPS32R2-LABEL: shl_i64: ; MIPS32R2: # %bb.0: # %entry ; MIPS32R2-NEXT: sllv $1, $4, $7 -; MIPS32R2-NEXT: not $2, $7 +; MIPS32R2-NEXT: xori $2, $7, 31 ; MIPS32R2-NEXT: srl $3, $5, 1 ; MIPS32R2-NEXT: srlv $2, $3, $2 ; MIPS32R2-NEXT: or $2, $1, $2 @@ -382,7 +382,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { ; MIPS32R6-LABEL: shl_i64: ; MIPS32R6: # %bb.0: # %entry ; MIPS32R6-NEXT: sllv $1, $4, $7 -; MIPS32R6-NEXT: not $2, $7 +; MIPS32R6-NEXT: xori $2, $7, 31 ; MIPS32R6-NEXT: srl $3, $5, 1 ; MIPS32R6-NEXT: srlv $2, $3, $2 ; MIPS32R6-NEXT: or $1, $1, $2 @@ -422,9 +422,9 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { ; MMR3-LABEL: shl_i64: ; MMR3: # %bb.0: # %entry ; MMR3-NEXT: sllv $3, $4, $7 -; MMR3-NEXT: not16 $2, $7 -; MMR3-NEXT: srl16 $4, $5, 1 -; MMR3-NEXT: srlv $2, $4, $2 +; MMR3-NEXT: xori $1, $7, 31 +; MMR3-NEXT: srl16 $2, $5, 1 +; MMR3-NEXT: srlv $2, $2, $1 ; MMR3-NEXT: or16 $2, $3 ; MMR3-NEXT: sllv $3, $5, $7 ; MMR3-NEXT: andi16 $4, $7, 32 @@ -436,7 +436,7 @@ define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { ; MMR6-LABEL: shl_i64: ; MMR6: # %bb.0: # %entry ; MMR6-NEXT: sllv $1, $4, $7 -; MMR6-NEXT: not16 $2, $7 +; MMR6-NEXT: xori $2, $7, 31 ; MMR6-NEXT: srl16 $3, $5, 1 ; MMR6-NEXT: srlv $2, $3, $2 ; MMR6-NEXT: or $1, $1, $2 @@ -668,7 +668,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { ; MIPS3-NEXT: .LBB5_3: # %entry ; MIPS3-NEXT: dsllv $1, $4, $7 ; MIPS3-NEXT: dsrl $2, $5, 1 -; MIPS3-NEXT: not $3, $3 +; MIPS3-NEXT: xori $3, $3, 63 ; MIPS3-NEXT: dsrlv $2, $2, $3 ; MIPS3-NEXT: or $2, $1, $2 ; MIPS3-NEXT: bnez $8, .LBB5_2 @@ -682,7 +682,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { ; MIPS4-NEXT: dsllv $1, $4, $7 ; MIPS4-NEXT: dsrl $2, $5, 1 ; MIPS4-NEXT: sll $4, $7, 0 -; MIPS4-NEXT: not $3, $4 +; MIPS4-NEXT: xori $3, $4, 63 ; MIPS4-NEXT: dsrlv $2, $2, $3 ; MIPS4-NEXT: or $2, $1, $2 ; MIPS4-NEXT: dsllv $3, $5, $7 @@ -696,7 +696,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { ; MIPS64-NEXT: dsllv $1, $4, $7 ; MIPS64-NEXT: dsrl $2, $5, 1 ; MIPS64-NEXT: sll $4, $7, 0 -; MIPS64-NEXT: not $3, $4 +; MIPS64-NEXT: xori $3, $4, 63 ; MIPS64-NEXT: dsrlv $2, $2, $3 ; MIPS64-NEXT: or $2, $1, $2 ; MIPS64-NEXT: dsllv $3, $5, $7 @@ -710,7 +710,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { ; MIPS64R2-NEXT: dsllv $1, $4, $7 ; MIPS64R2-NEXT: dsrl $2, $5, 1 ; MIPS64R2-NEXT: sll $4, $7, 0 -; MIPS64R2-NEXT: not $3, $4 +; MIPS64R2-NEXT: xori $3, $4, 63 ; MIPS64R2-NEXT: dsrlv $2, $2, $3 ; MIPS64R2-NEXT: or $2, $1, $2 ; MIPS64R2-NEXT: dsllv $3, $5, $7 @@ -724,7 +724,7 @@ define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { ; MIPS64R6-NEXT: dsllv $1, $4, $7 ; MIPS64R6-NEXT: dsrl $2, $5, 1 ; MIPS64R6-NEXT: sll $3, $7, 0 -; MIPS64R6-NEXT: not $4, $3 +; MIPS64R6-NEXT: xori $4, $3, 63 ; MIPS64R6-NEXT: dsrlv $2, $2, $4 ; MIPS64R6-NEXT: or $1, $1, $2 ; MIPS64R6-NEXT: andi $2, $3, 64 From 3d1cae6699f9fde0dcd2274ea92cacf8ce4b757b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 3 Nov 2023 09:51:32 -0700 Subject: [PATCH 2/2] Adjust comments. --- llvm/lib/Target/Mips/MipsISelLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index dbc790c5663fd..f09d52aa5fd64 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -2593,7 +2593,7 @@ SDValue MipsTargetLowering::lowerShiftLeftParts(SDValue Op, SDValue Shamt = Op.getOperand(2); // if shamt < (VT.bits): // lo = (shl lo, shamt) - // hi = (or (shl hi, shamt) (srl (srl lo, 1), (VT.bits-1) ^ shamt)) + // hi = (or (shl hi, shamt) (srl (srl lo, 1), (xor shamt, (VT.bits-1)))) // else: // lo = 0 // hi = (shl lo, shamt[4:0]) @@ -2624,7 +2624,7 @@ SDValue MipsTargetLowering::lowerShiftRightParts(SDValue Op, SelectionDAG &DAG, MVT VT = Subtarget.isGP64bit() ? MVT::i64 : MVT::i32; // if shamt < (VT.bits): - // lo = (or (shl (shl hi, 1), (VT.bits-1) ^ shamt) (srl lo, shamt)) + // lo = (or (shl (shl hi, 1), (xor shamt, (VT.bits-1))) (srl lo, shamt)) // if isSRA: // hi = (sra hi, shamt) // else: