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[RISCV] Sink code into using branch in shuffle lowering [nfc]
Follow up to 396b6bb, sink code into consuming branch, and fix one comment I realized used the misleading wording. (Permute is a specific sub-type of single source shuffle.)
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -4998,32 +4998,32 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
49984998
MVT MaskVT = MVT::getVectorVT(MVT::i1, NumElts);
49994999
SDValue SelectMask = DAG.getBuildVector(MaskVT, DL, MaskVals);
50005000

5001-
unsigned GatherVVOpc = RISCVISD::VRGATHER_VV_VL;
5002-
MVT IndexVT = VT.changeTypeToInteger();
5003-
// Since we can't introduce illegal index types at this stage, use i16 and
5004-
// vrgatherei16 if the corresponding index type for plain vrgather is greater
5005-
// than XLenVT.
5006-
if (IndexVT.getScalarType().bitsGT(XLenVT)) {
5007-
GatherVVOpc = RISCVISD::VRGATHEREI16_VV_VL;
5008-
IndexVT = IndexVT.changeVectorElementType(MVT::i16);
5009-
}
5010-
5011-
// If the mask allows, we can do all the index computation in 16 bits. This
5012-
// requires less work and less register pressure at high LMUL, and creates
5013-
// smaller constants which may be cheaper to materialize.
5014-
if (IndexVT.getScalarType().bitsGT(MVT::i16) && isUInt<16>(NumElts - 1) &&
5015-
(IndexVT.getSizeInBits() / Subtarget.getRealMinVLen()) > 1) {
5016-
GatherVVOpc = RISCVISD::VRGATHEREI16_VV_VL;
5017-
IndexVT = IndexVT.changeVectorElementType(MVT::i16);
5018-
}
5019-
5020-
MVT IndexContainerVT =
5021-
ContainerVT.changeVectorElementType(IndexVT.getScalarType());
5022-
50235001
// Base case for the recursion just below - handle the worst case
50245002
// single source permutation. Note that all the splat variants
50255003
// are handled above.
50265004
if (V2.isUndef()) {
5005+
unsigned GatherVVOpc = RISCVISD::VRGATHER_VV_VL;
5006+
MVT IndexVT = VT.changeTypeToInteger();
5007+
// Since we can't introduce illegal index types at this stage, use i16 and
5008+
// vrgatherei16 if the corresponding index type for plain vrgather is greater
5009+
// than XLenVT.
5010+
if (IndexVT.getScalarType().bitsGT(XLenVT)) {
5011+
GatherVVOpc = RISCVISD::VRGATHEREI16_VV_VL;
5012+
IndexVT = IndexVT.changeVectorElementType(MVT::i16);
5013+
}
5014+
5015+
// If the mask allows, we can do all the index computation in 16 bits. This
5016+
// requires less work and less register pressure at high LMUL, and creates
5017+
// smaller constants which may be cheaper to materialize.
5018+
if (IndexVT.getScalarType().bitsGT(MVT::i16) && isUInt<16>(NumElts - 1) &&
5019+
(IndexVT.getSizeInBits() / Subtarget.getRealMinVLen()) > 1) {
5020+
GatherVVOpc = RISCVISD::VRGATHEREI16_VV_VL;
5021+
IndexVT = IndexVT.changeVectorElementType(MVT::i16);
5022+
}
5023+
5024+
MVT IndexContainerVT =
5025+
ContainerVT.changeVectorElementType(IndexVT.getScalarType());
5026+
50275027
V1 = convertToScalableVector(ContainerVT, V1, DAG, Subtarget);
50285028
SmallVector<SDValue> GatherIndicesLHS;
50295029
for (int ShuffleIdx : ShuffleMaskLHS)
@@ -5039,7 +5039,7 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
50395039
}
50405040

50415041
// Recursively invoke lowering for each operand if we had two
5042-
// independent single source permutes, and then combine the result via a
5042+
// independent single source shuffles, and then combine the result via a
50435043
// vselect. Note that the vselect will likely be folded back into the
50445044
// second permute (vrgather, or other) by the post-isel combine.
50455045
V1 = DAG.getVectorShuffle(VT, DL, V1, DAG.getUNDEF(VT), ShuffleMaskLHS);

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