[MC] Make MCRegisterInfo::getLLVMRegNum return std::optional<MCRegister>. NFC (#107776)

Author: topperc

llvm/include/llvm/MC/MCRegisterInfo.h

@@ -420,9 +420,9 @@ class MCRegisterInfo {
   /// debugging info.
   int getDwarfRegNum(MCRegister RegNum, bool isEH) const;
 
-  /// Map a dwarf register back to a target register. Returns std::nullopt is
+  /// Map a dwarf register back to a target register. Returns std::nullopt if
   /// there is no mapping.
-  std::optional<unsigned> getLLVMRegNum(unsigned RegNum, bool isEH) const;
+  std::optional<MCRegister> getLLVMRegNum(unsigned RegNum, bool isEH) const;
 
   /// Map a target EH register number to an equivalent DWARF register
   /// number.

llvm/lib/CodeGen/MachineOperand.cpp

@@ -494,7 +494,7 @@ static void printCFIRegister(unsigned DwarfReg, raw_ostream &OS,
     return;
   }
 
-  if (std::optional<unsigned> Reg = TRI->getLLVMRegNum(DwarfReg, true))
+  if (std::optional<MCRegister> Reg = TRI->getLLVMRegNum(DwarfReg, true))
     OS << printReg(*Reg, TRI);
   else
     OS << "<badreg>";

llvm/lib/CodeGen/StackMaps.cpp

@@ -282,7 +282,7 @@ StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
 
     unsigned Offset = 0;
     unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI);
-    unsigned LLVMRegNum = *TRI->getLLVMRegNum(DwarfRegNum, false);
+    MCRegister LLVMRegNum = *TRI->getLLVMRegNum(DwarfRegNum, false);
     unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg());
     if (SubRegIdx)
       Offset = TRI->getSubRegIdxOffset(SubRegIdx);

llvm/lib/DebugInfo/LogicalView/Readers/LVDWARFReader.cpp

@@ -789,7 +789,7 @@ std::string LVDWARFReader::getRegisterName(LVSmall Opcode,
   auto GetRegName = [&MCRegInfo](uint64_t DwarfRegNum, bool IsEH) -> StringRef {
     if (!MCRegInfo)
       return {};
-    if (std::optional<unsigned> LLVMRegNum =
+    if (std::optional<MCRegister> LLVMRegNum =
             MCRegInfo->getLLVMRegNum(DwarfRegNum, IsEH))
       if (const char *RegName = MCRegInfo->getName(*LLVMRegNum))
         return StringRef(RegName);

llvm/lib/MC/MCAsmStreamer.cpp

@@ -1971,7 +1971,7 @@ void MCAsmStreamer::EmitRegisterName(int64_t Register) {
     // just ones that map to LLVM register numbers and have known names.
     // Fall back to using the original number directly if no name is known.
     const MCRegisterInfo *MRI = getContext().getRegisterInfo();
-    if (std::optional<unsigned> LLVMRegister =
+    if (std::optional<MCRegister> LLVMRegister =
             MRI->getLLVMRegNum(Register, true)) {
       InstPrinter->printRegName(OS, *LLVMRegister);
       return;

llvm/lib/MC/MCRegisterInfo.cpp

@@ -154,8 +154,8 @@ int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
   return I->ToReg;
 }
 
-std::optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum,
-                                                      bool isEH) const {
+std::optional<MCRegister> MCRegisterInfo::getLLVMRegNum(unsigned RegNum,
+                                                        bool isEH) const {
   const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
   unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
 
@@ -164,7 +164,7 @@ std::optional<unsigned> MCRegisterInfo::getLLVMRegNum(unsigned RegNum,
   DwarfLLVMRegPair Key = { RegNum, 0 };
   const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
   if (I != M + Size && I->FromReg == RegNum)
-    return I->ToReg;
+    return MCRegister::from(I->ToReg);
   return std::nullopt;
 }
 
@@ -177,7 +177,7 @@ int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const {
   // a corresponding LLVM register number at all.  So if we can't map the
   // EH register number to an LLVM register number, assume it's just a
   // valid DWARF register number as is.
-  if (std::optional<unsigned> LRegNum = getLLVMRegNum(RegNum, true)) {
+  if (std::optional<MCRegister> LRegNum = getLLVMRegNum(RegNum, true)) {
     int DwarfRegNum = getDwarfRegNum(*LRegNum, false);
     if (DwarfRegNum == -1)
       return RegNum;

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

@@ -646,8 +646,8 @@ class DarwinAArch64AsmBackend : public AArch64AsmBackend {
           return CU::UNWIND_ARM64_MODE_DWARF;
         CurOffset = FPPush.getOffset();
 
-        unsigned LRReg = *MRI.getLLVMRegNum(LRPush.getRegister(), true);
-        unsigned FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true);
+        MCRegister LRReg = *MRI.getLLVMRegNum(LRPush.getRegister(), true);
+        MCRegister FPReg = *MRI.getLLVMRegNum(FPPush.getRegister(), true);
 
         LRReg = getXRegFromWReg(LRReg);
         FPReg = getXRegFromWReg(FPReg);
@@ -669,7 +669,7 @@ class DarwinAArch64AsmBackend : public AArch64AsmBackend {
       case MCCFIInstruction::OpOffset: {
         // Registers are saved in pairs. We expect there to be two consecutive
         // `.cfi_offset' instructions with the appropriate registers specified.
-        unsigned Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true);
+        MCRegister Reg1 = *MRI.getLLVMRegNum(Inst.getRegister(), true);
         if (i + 1 == e)
           return CU::UNWIND_ARM64_MODE_DWARF;
 
@@ -680,7 +680,7 @@ class DarwinAArch64AsmBackend : public AArch64AsmBackend {
         const MCCFIInstruction &Inst2 = Instrs[++i];
         if (Inst2.getOperation() != MCCFIInstruction::OpOffset)
           return CU::UNWIND_ARM64_MODE_DWARF;
-        unsigned Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true);
+        MCRegister Reg2 = *MRI.getLLVMRegNum(Inst2.getRegister(), true);
 
         if (Inst2.getOffset() != CurOffset - 8)
           return CU::UNWIND_ARM64_MODE_DWARF;

llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

@@ -1185,14 +1185,14 @@ uint64_t ARMAsmBackendDarwin::generateCompactUnwindEncoding(
     return CU::UNWIND_ARM_MODE_DWARF;
 
   // Start off assuming CFA is at SP+0.
-  unsigned CFARegister = ARM::SP;
+  MCRegister CFARegister = ARM::SP;
   int CFARegisterOffset = 0;
   // Mark savable registers as initially unsaved
   DenseMap<unsigned, int> RegOffsets;
   int FloatRegCount = 0;
   // Process each .cfi directive and build up compact unwind info.
   for (const MCCFIInstruction &Inst : Instrs) {
-    unsigned Reg;
+    MCRegister Reg;
     switch (Inst.getOperation()) {
     case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa
       CFARegisterOffset = Inst.getOffset();

llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp

@@ -1412,7 +1412,7 @@ class DarwinX86AsmBackend : public X86AsmBackend {
           // unwind encoding.
           return CU::UNWIND_MODE_DWARF;
 
-        unsigned Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);
+        MCRegister Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true);
         SavedRegs[SavedRegIdx++] = Reg;
         StackAdjust += OffsetSize;
         MinAbsOffset = std::min(MinAbsOffset, std::abs(Inst.getOffset()));