Skip to content

Commit dedf014

Browse files
tangaacSixWeining
tangaac
and
SixWeining
authored
[LoongArch] lower SCALAR_TO_VECTOR to INSERT_VECTOR_ELT (#122863)
```llvm define <16 x i8> @scalar_to_16xi8(i8 %val) { %ret = insertelement <16 x i8> undef, i8 %val, i32 0 ret <16 x i8> %ret } ``` before ```asm addi.d $sp, $sp, -16 st.b $a0, $sp, 0 vld $vr0, $sp, 0 addi.d $sp, $sp, 16 ret ``` after ```asm vinsgr2vr.b $vr0, $a0, 0 ret ``` --------- Co-authored-by: Lu Weining <[email protected]>
1 parent 2b0e225 commit dedf014

8 files changed

+150
-9
lines changed

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -271,6 +271,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
271271
setCondCodeAction(
272272
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
273273
Expand);
274+
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
274275
}
275276
for (MVT VT : {MVT::v16i8, MVT::v8i16, MVT::v4i32})
276277
setOperationAction(ISD::BITREVERSE, VT, Custom);
@@ -289,6 +290,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
289290
setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
290291
ISD::SETUGE, ISD::SETUGT},
291292
VT, Expand);
293+
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
292294
}
293295
setOperationAction(ISD::CTPOP, GRLenVT, Legal);
294296
setOperationAction(ISD::FCEIL, {MVT::f32, MVT::f64}, Legal);
@@ -327,6 +329,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
327329
setCondCodeAction(
328330
{ISD::SETNE, ISD::SETGE, ISD::SETGT, ISD::SETUGE, ISD::SETUGT}, VT,
329331
Expand);
332+
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
330333
}
331334
for (MVT VT : {MVT::v32i8, MVT::v16i16, MVT::v8i32})
332335
setOperationAction(ISD::BITREVERSE, VT, Custom);
@@ -345,6 +348,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
345348
setCondCodeAction({ISD::SETGE, ISD::SETGT, ISD::SETOGE, ISD::SETOGT,
346349
ISD::SETUGE, ISD::SETUGT},
347350
VT, Expand);
351+
setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Legal);
348352
}
349353
}
350354

@@ -448,10 +452,25 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
448452
return lowerVECTOR_SHUFFLE(Op, DAG);
449453
case ISD::BITREVERSE:
450454
return lowerBITREVERSE(Op, DAG);
455+
case ISD::SCALAR_TO_VECTOR:
456+
return lowerSCALAR_TO_VECTOR(Op, DAG);
451457
}
452458
return SDValue();
453459
}
454460

461+
SDValue
462+
LoongArchTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
463+
SelectionDAG &DAG) const {
464+
SDLoc DL(Op);
465+
MVT OpVT = Op.getSimpleValueType();
466+
467+
SDValue Vector = DAG.getUNDEF(OpVT);
468+
SDValue Val = Op.getOperand(0);
469+
SDValue Idx = DAG.getConstant(0, DL, Subtarget.getGRLenVT());
470+
471+
return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, OpVT, Vector, Val, Idx);
472+
}
473+
455474
SDValue LoongArchTargetLowering::lowerBITREVERSE(SDValue Op,
456475
SelectionDAG &DAG) const {
457476
EVT ResTy = Op->getValueType(0);

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -336,6 +336,7 @@ class LoongArchTargetLowering : public TargetLowering {
336336
SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
337337
SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
338338
SDValue lowerBITREVERSE(SDValue Op, SelectionDAG &DAG) const;
339+
SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
339340

340341
bool isFPImmLegal(const APFloat &Imm, EVT VT,
341342
bool ForCodeSize) const override;

‎llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1562,6 +1562,12 @@ def : Pat<(vector_insert v8f32:$vd, FPR32:$fj, uimm3:$imm),
15621562
def : Pat<(vector_insert v4f64:$vd, FPR64:$fj, uimm2:$imm),
15631563
(XVINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm2:$imm)>;
15641564

1565+
// scalar_to_vector
1566+
def : Pat<(v8f32 (scalar_to_vector FPR32:$fj)),
1567+
(SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>;
1568+
def : Pat<(v4f64 (scalar_to_vector FPR64:$fj)),
1569+
(SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>;
1570+
15651571
// XVPICKVE2GR_W[U]
15661572
def : Pat<(loongarch_vpick_sext_elt v8i32:$xd, uimm3:$imm, i32),
15671573
(XVPICKVE2GR_W v8i32:$xd, uimm3:$imm)>;

‎llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1719,6 +1719,12 @@ def : Pat<(vector_insert v4f32:$vd, FPR32:$fj, uimm2:$imm),
17191719
def : Pat<(vector_insert v2f64:$vd, FPR64:$fj, uimm1:$imm),
17201720
(VINSGR2VR_D $vd, (COPY_TO_REGCLASS FPR64:$fj, GPR), uimm1:$imm)>;
17211721

1722+
// scalar_to_vector
1723+
def : Pat<(v4f32 (scalar_to_vector FPR32:$fj)),
1724+
(SUBREG_TO_REG (i64 0), FPR32:$fj, sub_32)>;
1725+
def : Pat<(v2f64 (scalar_to_vector FPR64:$fj)),
1726+
(SUBREG_TO_REG (i64 0), FPR64:$fj, sub_64)>;
1727+
17221728
// VPICKVE2GR_{B/H/W}[U]
17231729
def : Pat<(loongarch_vpick_sext_elt v16i8:$vd, uimm4:$imm, i8),
17241730
(VPICKVE2GR_B v16i8:$vd, uimm4:$imm)>;

‎llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
3+
4+
;; Test scalar_to_vector expansion.
5+
6+
define <32 x i8> @scalar_to_32xi8(i8 %val) {
7+
; CHECK-LABEL: scalar_to_32xi8:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
10+
; CHECK-NEXT: ret
11+
%ret = insertelement <32 x i8> poison, i8 %val, i32 0
12+
ret <32 x i8> %ret
13+
}
14+
15+
define <16 x i16> @scalar_to_16xi16(i16 %val) {
16+
; CHECK-LABEL: scalar_to_16xi16:
17+
; CHECK: # %bb.0:
18+
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
19+
; CHECK-NEXT: ret
20+
%ret = insertelement <16 x i16> poison, i16 %val, i32 0
21+
ret <16 x i16> %ret
22+
}
23+
24+
define <8 x i32> @scalar_to_8xi32(i32 %val) {
25+
; CHECK-LABEL: scalar_to_8xi32:
26+
; CHECK: # %bb.0:
27+
; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 0
28+
; CHECK-NEXT: ret
29+
%ret = insertelement <8 x i32> poison, i32 %val, i32 0
30+
ret <8 x i32> %ret
31+
}
32+
33+
define <4 x i64> @scalar_to_4xi64(i64 %val) {
34+
; CHECK-LABEL: scalar_to_4xi64:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0
37+
; CHECK-NEXT: ret
38+
%ret = insertelement <4 x i64> poison, i64 %val, i32 0
39+
ret <4 x i64> %ret
40+
}
41+
42+
define <8 x float> @scalar_to_8xf32(float %val) {
43+
; CHECK-LABEL: scalar_to_8xf32:
44+
; CHECK: # %bb.0:
45+
; CHECK-NEXT: # kill: def $f0 killed $f0 def $xr0
46+
; CHECK-NEXT: ret
47+
%ret = insertelement <8 x float> poison, float %val, i32 0
48+
ret <8 x float> %ret
49+
}
50+
51+
define <4 x double> @scalar_to_4xf64(double %val) {
52+
; CHECK-LABEL: scalar_to_4xf64:
53+
; CHECK: # %bb.0:
54+
; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $xr0
55+
; CHECK-NEXT: ret
56+
%ret = insertelement <4 x double> poison, double %val, i32 0
57+
ret <4 x double> %ret
58+
}

‎llvm/test/CodeGen/LoongArch/lsx/build-vector.ll

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -369,19 +369,15 @@ entry:
369369
ret void
370370
}
371371

372-
;; BUILD_VECTOR through stack.
373372
;; If `isShuffleMaskLegal` returns true, it will lead to an infinite loop.
374373
define void @extract1_i32_zext_insert0_i64_undef(ptr %src, ptr %dst) nounwind {
375374
; CHECK-LABEL: extract1_i32_zext_insert0_i64_undef:
376375
; CHECK: # %bb.0:
377-
; CHECK-NEXT: addi.d $sp, $sp, -16
378376
; CHECK-NEXT: vld $vr0, $a0, 0
379377
; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 1
380378
; CHECK-NEXT: bstrpick.d $a0, $a0, 31, 0
381-
; CHECK-NEXT: st.d $a0, $sp, 0
382-
; CHECK-NEXT: vld $vr0, $sp, 0
379+
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
383380
; CHECK-NEXT: vst $vr0, $a1, 0
384-
; CHECK-NEXT: addi.d $sp, $sp, 16
385381
; CHECK-NEXT: ret
386382
%v = load volatile <4 x i32>, ptr %src
387383
%e = extractelement <4 x i32> %v, i32 1

‎llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
2+
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
3+
4+
;; Test scalar_to_vector expansion.
5+
6+
define <16 x i8> @scalar_to_16xi8(i8 %val) {
7+
; CHECK-LABEL: scalar_to_16xi8:
8+
; CHECK: # %bb.0:
9+
; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
10+
; CHECK-NEXT: ret
11+
%ret = insertelement <16 x i8> poison, i8 %val, i32 0
12+
ret <16 x i8> %ret
13+
}
14+
15+
define <8 x i16> @scalar_to_8xi16(i16 %val) {
16+
; CHECK-LABEL: scalar_to_8xi16:
17+
; CHECK: # %bb.0:
18+
; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
19+
; CHECK-NEXT: ret
20+
%ret = insertelement <8 x i16> poison, i16 %val, i32 0
21+
ret <8 x i16> %ret
22+
}
23+
24+
define <4 x i32> @scalar_to_4xi32(i32 %val) {
25+
; CHECK-LABEL: scalar_to_4xi32:
26+
; CHECK: # %bb.0:
27+
; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
28+
; CHECK-NEXT: ret
29+
%ret = insertelement <4 x i32> poison, i32 %val, i32 0
30+
ret <4 x i32> %ret
31+
}
32+
33+
define <2 x i64> @scalar_to_2xi64(i64 %val) {
34+
; CHECK-LABEL: scalar_to_2xi64:
35+
; CHECK: # %bb.0:
36+
; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
37+
; CHECK-NEXT: ret
38+
%ret = insertelement <2 x i64> poison, i64 %val, i32 0
39+
ret <2 x i64> %ret
40+
}
41+
42+
define <4 x float> @scalar_to_4xf32(float %val) {
43+
; CHECK-LABEL: scalar_to_4xf32:
44+
; CHECK: # %bb.0:
45+
; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0
46+
; CHECK-NEXT: ret
47+
%ret = insertelement <4 x float> poison, float %val, i32 0
48+
ret <4 x float> %ret
49+
}
50+
51+
define <2 x double> @scalar_to_2xf64(double %val) {
52+
; CHECK-LABEL: scalar_to_2xf64:
53+
; CHECK: # %bb.0:
54+
; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0
55+
; CHECK-NEXT: ret
56+
%ret = insertelement <2 x double> poison, double %val, i32 0
57+
ret <2 x double> %ret
58+
}

‎llvm/test/CodeGen/LoongArch/vector-fp-imm.ll

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -126,17 +126,14 @@ define void @test_f2(ptr %P, ptr %S) nounwind {
126126
;
127127
; LA64D-LABEL: test_f2:
128128
; LA64D: # %bb.0:
129-
; LA64D-NEXT: addi.d $sp, $sp, -16
130129
; LA64D-NEXT: ld.d $a0, $a0, 0
131-
; LA64D-NEXT: st.d $a0, $sp, 0
132-
; LA64D-NEXT: vld $vr0, $sp, 0
130+
; LA64D-NEXT: vinsgr2vr.d $vr0, $a0, 0
133131
; LA64D-NEXT: lu12i.w $a0, 260096
134132
; LA64D-NEXT: lu52i.d $a0, $a0, 1024
135133
; LA64D-NEXT: vreplgr2vr.d $vr1, $a0
136134
; LA64D-NEXT: vfadd.s $vr0, $vr0, $vr1
137135
; LA64D-NEXT: vpickve2gr.d $a0, $vr0, 0
138136
; LA64D-NEXT: st.d $a0, $a1, 0
139-
; LA64D-NEXT: addi.d $sp, $sp, 16
140137
; LA64D-NEXT: ret
141138
%p = load %f2, ptr %P
142139
%R = fadd %f2 %p, < float 1.000000e+00, float 2.000000e+00 >

0 commit comments

Comments
 (0)