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[RISCV] Swap the order of SEWGreaterThanOrEqualAndLessThan64 and SEWGreaterThanOrEqual. (#120649)
SEWGreaterThanOrEqualAndLessThan64 is a stricter constraint so it should have a higher value than SEWGreaterThanOrEqual. Found by our random test generator.
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+47
-7
lines changed

2 files changed

+47
-7
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llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -218,14 +218,14 @@ struct DemandedFields {
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bool VLZeroness = false;
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// What properties of SEW we need to preserve.
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enum : uint8_t {
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SEWEqual = 3, // The exact value of SEW needs to be preserved.
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SEWGreaterThanOrEqual = 2, // SEW can be changed as long as it's greater
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// than or equal to the original value.
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SEWEqual = 3, // The exact value of SEW needs to be preserved.
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SEWGreaterThanOrEqualAndLessThan64 =
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1, // SEW can be changed as long as it's greater
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// than or equal to the original value, but must be less
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// than 64.
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SEWNone = 0 // We don't need to preserve SEW at all.
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2, // SEW can be changed as long as it's greater
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// than or equal to the original value, but must be less
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// than 64.
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SEWGreaterThanOrEqual = 1, // SEW can be changed as long as it's greater
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// than or equal to the original value.
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SEWNone = 0 // We don't need to preserve SEW at all.
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} SEW = SEWNone;
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enum : uint8_t {
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LMULEqual = 2, // The exact value of LMUL needs to be preserved.
Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,40 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc %s -mtriple=riscv64 -mattr=+zve64f -run-pass=riscv-insert-vsetvli -o - | FileCheck %s
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---
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name: spam
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tracksRegLiveness: true
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noPhis: true
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isSSA: false
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body: |
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bb.0.entry:
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liveins: $x10, $x11, $x12, $f10_f
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; CHECK-LABEL: name: spam
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; CHECK: liveins: $x10, $x11, $x12, $f10_f
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x12
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr32 = COPY $f10_f
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: renamable $v10 = PseudoVFMV_S_FPR32 undef renamable $v10, [[COPY3]], 8, 5 /* e32 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: renamable $v11 = PseudoVMV_S_X undef renamable $v11, [[COPY2]], 8, 5 /* e32 */, implicit $vl, implicit $vtype
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, [[COPY1]], 1, 6 /* e64 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 8)
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; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 8, 208 /* e32, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
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; CHECK-NEXT: renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, [[COPY]], 8, 5 /* e32 */, 2 /* tu, ma */, implicit $vl, implicit $vtype :: (load unknown-size, align 4)
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; CHECK-NEXT: INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3145737 /* reguse:VR */, killed renamable $v10, 3145737 /* reguse:VR */, killed renamable $v11, 3145737 /* reguse:VR */, killed renamable $v8, 3145737 /* reguse:VR */, killed renamable $v9
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; CHECK-NEXT: PseudoRET
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%3:gpr = COPY $x12
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%2:gpr = COPY $x11
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%1:gpr = COPY $x10
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%0:fpr32 = COPY $f10_f
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renamable $v10 = PseudoVFMV_S_FPR32 undef renamable $v10, %0, 8, 5 /* e32 */
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renamable $v11 = PseudoVMV_S_X undef renamable $v11, %1, 8, 5 /* e32 */
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renamable $v8 = PseudoVLE64_V_M1 undef renamable $v8, %2, 1, 6 /* e64 */, 2 /* tu, ma */ :: (load unknown-size, align 8)
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renamable $v9 = PseudoVLE32_V_M1 undef renamable $v9, %3, 8, 5 /* e32 */, 2 /* tu, ma */ :: (load unknown-size, align 4)
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INLINEASM &"# use $0 $1 $2 $3", 1 /* sideeffect attdialect */, 3145737 /* reguse:VR */, killed renamable $v10, 3145737 /* reguse:VR */, killed renamable $v11, 3145737 /* reguse:VR */, killed renamable $v8, 3145737 /* reguse:VR */, killed renamable $v9
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PseudoRET
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...

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