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[RISCV] Add an instruction PrettyPrinter to llvm-objdump (#90093)
This prints the opcode bytes in the same order as GNU objdump without a space between them.
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‎lld/test/ELF/riscv-branch.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -7,19 +7,19 @@
77
# RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64
88
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32
99
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64
10-
# CHECK-32: 63 02 00 00 beqz zero, 0x110b8
11-
# CHECK-32: e3 1e 00 fe bnez zero, 0x110b4
12-
# CHECK-64: 63 02 00 00 beqz zero, 0x11124
13-
# CHECK-64: e3 1e 00 fe bnez zero, 0x11120
10+
# CHECK-32: 00000263 beqz zero, 0x110b8
11+
# CHECK-32: fe001ee3 bnez zero, 0x110b4
12+
# CHECK-64: 00000263 beqz zero, 0x11124
13+
# CHECK-64: fe001ee3 bnez zero, 0x11120
1414
#
1515
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv32.limits
1616
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv64.limits
1717
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s
1818
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s
19-
# LIMITS-32: e3 0f 00 7e beqz zero, 0x120b2
20-
# LIMITS-32-NEXT: 63 10 00 80 bnez zero, 0x100b8
21-
# LIMITS-64: e3 0f 00 7e beqz zero, 0x1211e
22-
# LIMITS-64-NEXT: 63 10 00 80 bnez zero, 0x10124
19+
# LIMITS-32: 7e000fe3 beqz zero, 0x120b2
20+
# LIMITS-32-NEXT: 80001063 bnez zero, 0x100b8
21+
# LIMITS-64: 7e000fe3 beqz zero, 0x1211e
22+
# LIMITS-64-NEXT: 80001063 bnez zero, 0x10124
2323

2424
# RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
2525
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s

‎lld/test/ELF/riscv-call.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -7,19 +7,19 @@
77
# RUN: ld.lld %t.rv64.o --defsym foo=_start+8 --defsym bar=_start -o %t.rv64
88
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
99
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
10-
# CHECK: 97 00 00 00 auipc ra, 0x0
11-
# CHECK-NEXT: e7 80 80 00 jalr 0x8(ra)
12-
# CHECK: 97 00 00 00 auipc ra, 0x0
13-
# CHECK-NEXT: e7 80 80 ff jalr -0x8(ra)
10+
# CHECK: 00000097 auipc ra, 0x0
11+
# CHECK-NEXT: 008080e7 jalr 0x8(ra)
12+
# CHECK: 00000097 auipc ra, 0x0
13+
# CHECK-NEXT: ff8080e7 jalr -0x8(ra)
1414

1515
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+8-0x80000800 -o %t.rv32.limits
1616
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+8-0x80000800 -o %t.rv64.limits
1717
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
1818
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
19-
# LIMITS: 97 f0 ff 7f auipc ra, 0x7ffff
20-
# LIMITS-NEXT: e7 80 f0 7f jalr 0x7ff(ra)
21-
# LIMITS-NEXT: 97 00 00 80 auipc ra, 0x80000
22-
# LIMITS-NEXT: e7 80 00 80 jalr -0x800(ra)
19+
# LIMITS: 7ffff097 auipc ra, 0x7ffff
20+
# LIMITS-NEXT: 7ff080e7 jalr 0x7ff(ra)
21+
# LIMITS-NEXT: 80000097 auipc ra, 0x80000
22+
# LIMITS-NEXT: 800080e7 jalr -0x800(ra)
2323

2424
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+8-0x80000801 -o %t
2525
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+8-0x80000801 -o /dev/null 2>&1 | \

‎lld/test/ELF/riscv-hi20-lo12.s

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -7,23 +7,23 @@
77
# RUN: ld.lld %t.rv64.o --defsym foo=0 --defsym bar=42 -o %t.rv64
88
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s
99
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s
10-
# CHECK: 37 05 00 00 lui a0, 0x0
11-
# CHECK-NEXT: 13 05 05 00 mv a0, a0
12-
# CHECK-NEXT: 23 20 a5 00 sw a0, 0x0(a0)
13-
# CHECK-NEXT: b7 05 00 00 lui a1, 0x0
14-
# CHECK-NEXT: 93 85 a5 02 addi a1, a1, 0x2a
15-
# CHECK-NEXT: 23 a5 b5 02 sw a1, 0x2a(a1)
10+
# CHECK: 00000537 lui a0, 0x0
11+
# CHECK-NEXT: 00050513 mv a0, a0
12+
# CHECK-NEXT: 00a52023 sw a0, 0x0(a0)
13+
# CHECK-NEXT: 000005b7 lui a1, 0x0
14+
# CHECK-NEXT: 02a58593 addi a1, a1, 0x2a
15+
# CHECK-NEXT: 02b5a523 sw a1, 0x2a(a1)
1616

1717
# RUN: ld.lld %t.rv32.o --defsym foo=0x7ffff7ff --defsym bar=0x7ffff800 -o %t.rv32.limits
1818
# RUN: ld.lld %t.rv64.o --defsym foo=0x7ffff7ff --defsym bar=0xffffffff7ffff800 -o %t.rv64.limits
1919
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s
2020
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s
21-
# LIMITS: 37 f5 ff 7f lui a0, 0x7ffff
22-
# LIMITS-NEXT: 13 05 f5 7f addi a0, a0, 0x7ff
23-
# LIMITS-NEXT: a3 2f a5 7e sw a0, 0x7ff(a0)
24-
# LIMITS-NEXT: b7 05 00 80 lui a1, 0x80000
25-
# LIMITS-NEXT: 93 85 05 80 addi a1, a1, -0x800
26-
# LIMITS-NEXT: 23 a0 b5 80 sw a1, -0x800(a1)
21+
# LIMITS: 7ffff537 lui a0, 0x7ffff
22+
# LIMITS-NEXT: 7ff50513 addi a0, a0, 0x7ff
23+
# LIMITS-NEXT: 7ea52fa3 sw a0, 0x7ff(a0)
24+
# LIMITS-NEXT: 800005b7 lui a1, 0x80000
25+
# LIMITS-NEXT: 80058593 addi a1, a1, -0x800
26+
# LIMITS-NEXT: 80b5a023 sw a1, -0x800(a1)
2727

2828
# RUN: not ld.lld %t.rv64.o --defsym foo=0x7ffff800 --defsym bar=0xffffffff7ffff7ff -o /dev/null 2>&1 | FileCheck --check-prefix ERROR %s
2929
# ERROR: relocation R_RISCV_HI20 out of range: 524288 is not in [-524288, 524287]; references 'foo'

‎lld/test/ELF/riscv-jal.s

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -7,19 +7,19 @@
77
# RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64
88
# RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32
99
# RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64
10-
# CHECK-32: 6f 00 40 00 j 0x110b8
11-
# CHECK-32: ef f0 df ff jal 0x110b4
12-
# CHECK-64: 6f 00 40 00 j 0x11124
13-
# CHECK-64: ef f0 df ff jal 0x11120
10+
# CHECK-32: 0040006f j 0x110b8
11+
# CHECK-32: ffdff0ef jal 0x110b4
12+
# CHECK-64: 0040006f j 0x11124
13+
# CHECK-64: ffdff0ef jal 0x11120
1414

1515
# RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv32.limits
1616
# RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv64.limits
1717
# RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s
1818
# RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s
19-
# LIMITS-32: 6f f0 ff 7f j 0x1110b2
20-
# LIMITS-32-NEXT: ef 00 00 80 jal 0xfff110b8
21-
# LIMITS-64: 6f f0 ff 7f j 0x11111e
22-
# LIMITS-64-NEXT: ef 00 00 80 jal 0xfffffffffff11124
19+
# LIMITS-32: 7ffff06f j 0x1110b2
20+
# LIMITS-32-NEXT: 800000ef jal 0xfff110b8
21+
# LIMITS-64: 7ffff06f j 0x11111e
22+
# LIMITS-64-NEXT: 800000ef jal 0xfffffffffff11124
2323

2424
# RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s
2525
# RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s

‎llvm/docs/ReleaseNotes.rst

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,6 +113,8 @@ Changes to the RISC-V Backend
113113
* The experimental Ssqosid extension is supported.
114114
* Zacas is no longer experimental.
115115
* Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi) extension.
116+
* llvm-objdump now prints disassembled opcode bytes in groups of 2 or 4 bytes to
117+
match GNU objdump. The bytes within the groups are in big endian order.
116118

117119
Changes to the WebAssembly Backend
118120
----------------------------------

‎llvm/test/MC/RISCV/XTHeadVdot-valid.s

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -12,82 +12,82 @@ th.vmaqau.vv v8, v20, v4, v0.t
1212
# CHECK-INST: th.vmaqau.vv v8, v20, v4, v0.t
1313
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x88]
1414
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
15-
# CHECK-UNKNOWN: 0b 64 4a 88 <unknown>
15+
# CHECK-UNKNOWN: 884a640b <unknown>
1616

1717
th.vmaqau.vv v8, v20, v4
1818
# CHECK-INST: th.vmaqau.vv v8, v20, v4
1919
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x8a]
2020
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
21-
# CHECK-UNKNOWN: 0b 64 4a 8a <unknown>
21+
# CHECK-UNKNOWN: 8a4a640b <unknown>
2222

2323
th.vmaqau.vx v8, a0, v4, v0.t
2424
# CHECK-INST: th.vmaqau.vx v8, a0, v4, v0.t
2525
# CHECK-ENCODING: [0x0b,0x64,0x45,0x8c]
2626
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
27-
# CHECK-UNKNOWN: 0b 64 45 8c <unknown>
27+
# CHECK-UNKNOWN: 8c45640b <unknown>
2828

2929
th.vmaqau.vx v8, a0, v4
3030
# CHECK-INST: th.vmaqau.vx v8, a0, v4
3131
# CHECK-ENCODING: [0x0b,0x64,0x45,0x8e]
3232
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
33-
# CHECK-UNKNOWN: 0b 64 45 8e <unknown>
33+
# CHECK-UNKNOWN: 8e45640b <unknown>
3434

3535
th.vmaqa.vv v8, v20, v4, v0.t
3636
# CHECK-INST: th.vmaqa.vv v8, v20, v4, v0.t
3737
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x80]
3838
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
39-
# CHECK-UNKNOWN: 0b 64 4a 80 <unknown>
39+
# CHECK-UNKNOWN: 804a640b <unknown>
4040

4141
th.vmaqa.vv v8, v20, v4
4242
# CHECK-INST: th.vmaqa.vv v8, v20, v4
4343
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x82]
4444
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
45-
# CHECK-UNKNOWN: 0b 64 4a 82 <unknown>
45+
# CHECK-UNKNOWN: 824a640b <unknown>
4646

4747
th.vmaqa.vx v8, a0, v4, v0.t
4848
# CHECK-INST: th.vmaqa.vx v8, a0, v4, v0.t
4949
# CHECK-ENCODING: [0x0b,0x64,0x45,0x84]
5050
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
51-
# CHECK-UNKNOWN: 0b 64 45 84 <unknown>
51+
# CHECK-UNKNOWN: 8445640b <unknown>
5252

5353
th.vmaqa.vx v8, a0, v4
5454
# CHECK-INST: th.vmaqa.vx v8, a0, v4
5555
# CHECK-ENCODING: [0x0b,0x64,0x45,0x86]
5656
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
57-
# CHECK-UNKNOWN: 0b 64 45 86 <unknown>
57+
# CHECK-UNKNOWN: 8645640b <unknown>
5858

5959
th.vmaqasu.vv v8, v20, v4, v0.t
6060
# CHECK-INST: th.vmaqasu.vv v8, v20, v4, v0.t
6161
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x90]
6262
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
63-
# CHECK-UNKNOWN: 0b 64 4a 90 <unknown>
63+
# CHECK-UNKNOWN: 904a640b <unknown>
6464

6565
th.vmaqasu.vv v8, v20, v4
6666
# CHECK-INST: th.vmaqasu.vv v8, v20, v4
6767
# CHECK-ENCODING: [0x0b,0x64,0x4a,0x92]
6868
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
69-
# CHECK-UNKNOWN: 0b 64 4a 92 <unknown>
69+
# CHECK-UNKNOWN: 924a640b <unknown>
7070

7171
th.vmaqasu.vx v8, a0, v4, v0.t
7272
# CHECK-INST: th.vmaqasu.vx v8, a0, v4, v0.t
7373
# CHECK-ENCODING: [0x0b,0x64,0x45,0x94]
7474
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
75-
# CHECK-UNKNOWN: 0b 64 45 94 <unknown>
75+
# CHECK-UNKNOWN: 9445640b <unknown>
7676

7777
th.vmaqasu.vx v8, a0, v4
7878
# CHECK-INST: th.vmaqasu.vx v8, a0, v4
7979
# CHECK-ENCODING: [0x0b,0x64,0x45,0x96]
8080
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
81-
# CHECK-UNKNOWN: 0b 64 45 96 <unknown>
81+
# CHECK-UNKNOWN: 9645640b <unknown>
8282

8383
th.vmaqaus.vx v8, a0, v4, v0.t
8484
# CHECK-INST: th.vmaqaus.vx v8, a0, v4, v0.t
8585
# CHECK-ENCODING: [0x0b,0x64,0x45,0x9c]
8686
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
87-
# CHECK-UNKNOWN: 0b 64 45 9c <unknown>
87+
# CHECK-UNKNOWN: 9c45640b <unknown>
8888

8989
th.vmaqaus.vx v8, a0, v4
9090
# CHECK-INST: th.vmaqaus.vx v8, a0, v4
9191
# CHECK-ENCODING: [0x0b,0x64,0x45,0x9e]
9292
# CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}}
93-
# CHECK-UNKNOWN: 0b 64 45 9e <unknown>
93+
# CHECK-UNKNOWN: 9e45640b <unknown>

‎llvm/test/MC/RISCV/align.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -98,11 +98,11 @@ test:
9898
# The behavior is the same as GNU assembler.
9999
.p2align 4, 1
100100
# RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xC
101-
# RELAX-INST: 01 01
102-
# RELAX-INST: 01 01
101+
# RELAX-INST: 0101
102+
# RELAX-INST: 0101
103103
# C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xE
104-
# C-OR-ZCA-EXT-RELAX-INST: 01 01
105-
# C-EXT-INST: 01 01
104+
# C-OR-ZCA-EXT-RELAX-INST: 0101
105+
# C-EXT-INST: 0101
106106
ret
107107
# NORELAX-RELOC-NOT: R_RISCV
108108
# C-OR-ZCA-EXT-NORELAX-RELOC-NOT: R_RISCV

‎llvm/test/MC/RISCV/compress-cjal.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@
1111

1212
# c.jal is an rv32 only instruction.
1313
jal ra, 2046
14-
# CHECK-BYTES: fd 2f
14+
# CHECK-BYTES: 2ffd
1515
# CHECK-ALIASOBJ: jal 0x7fe
1616
# CHECK-ALIAS: jal 2046
1717
# CHECK-INST: c.jal 2046

‎llvm/test/MC/RISCV/compress-rv32d.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -43,22 +43,22 @@
4343
# Tests double precision floating point instructions available in rv32 and in rv64.
4444

4545
fld ft0, 64(sp)
46-
# CHECK-BYTES: 06 20
46+
# CHECK-BYTES: 2006
4747
# CHECK-ALIAS: fld ft0, 64(sp)
4848
# CHECK-INST: c.fldsp ft0, 64(sp)
4949
# CHECK: # encoding: [0x06,0x20]
5050
fsd ft0, 64(sp)
51-
# CHECK-BYTES: 82 a0
51+
# CHECK-BYTES: a082
5252
# CHECK-ALIAS: fsd ft0, 64(sp)
5353
# CHECK-INST: c.fsdsp ft0, 64(sp)
5454
# CHECK: # encoding: [0x82,0xa0]
5555
fld fs0, 248(s0)
56-
# CHECK-BYTES: 60 3c
56+
# CHECK-BYTES: 3c60
5757
# CHECK-ALIAS: fld fs0, 248(s0)
5858
# CHECK-INST: c.fld fs0, 248(s0)
5959
# CHECK: # encoding: [0x60,0x3c]
6060
fsd fs0, 248(s0)
61-
# CHECK-BYTES: 60 bc
61+
# CHECK-BYTES: bc60
6262
# CHECK-ALIAS: fsd fs0, 248(s0)
6363
# CHECK-INST: c.fsd fs0, 248(s0)
6464
# CHECK: # encoding: [0x60,0xbc]

‎llvm/test/MC/RISCV/compress-rv32f.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,22 +21,22 @@
2121

2222
# Instructions that are 32 bit only.
2323
flw ft0, 124(sp)
24-
# CHECK-BYTES: 76 70
24+
# CHECK-BYTES: 7076
2525
# CHECK-ALIAS: flw ft0, 124(sp)
2626
# CHECK-INST: c.flwsp ft0, 124(sp)
2727
# CHECK: # encoding: [0x76,0x70]
2828
fsw ft0, 124(sp)
29-
# CHECK-BYTES: 82 fe
29+
# CHECK-BYTES: fe82
3030
# CHECK-ALIAS: fsw ft0, 124(sp)
3131
# CHECK-INST: c.fswsp ft0, 124(sp)
3232
# CHECK: # encoding: [0x82,0xfe]
3333
flw fs0, 124(s0)
34-
# CHECK-BYTES: 60 7c
34+
# CHECK-BYTES: 7c60
3535
# CHECK-ALIAS: flw fs0, 124(s0)
3636
# CHECK-INST: c.flw fs0, 124(s0)
3737
# CHECK: # encoding: [0x60,0x7c]
3838
fsw fs0, 124(s0)
39-
# CHECK-BYTES: 60 fc
39+
# CHECK-BYTES: fc60
4040
# CHECK-ALIAS: fsw fs0, 124(s0)
4141
# CHECK-INST: c.fsw fs0, 124(s0)
4242
# CHECK: # encoding: [0x60,0xfc]

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