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AMDGPU/GlobalISel: Handle s64->s64 G_FPTOSI/G_FPTOUI
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‎llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1420,6 +1420,12 @@ class MachineIRBuilder {
14201420
return buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {Dst}, {Src0}, Flags);
14211421
}
14221422

1423+
/// Build and insert \p Res = GFFLOOR \p Op0, \p Op1
1424+
MachineInstrBuilder buildFFloor(const DstOp &Dst, const SrcOp &Src0,
1425+
Optional<unsigned> Flags = None) {
1426+
return buildInstr(TargetOpcode::G_FFLOOR, {Dst}, {Src0}, Flags);
1427+
}
1428+
14231429
/// Build and insert \p Dst = G_FLOG \p Src
14241430
MachineInstrBuilder buildFLog(const DstOp &Dst, const SrcOp &Src,
14251431
Optional<unsigned> Flags = None) {

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 42 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -457,7 +457,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
457457
.scalarize(0);
458458

459459
auto &FPToI = getActionDefinitionsBuilder({G_FPTOSI, G_FPTOUI})
460-
.legalFor({{S32, S32}, {S32, S64}, {S32, S16}});
460+
.legalFor({{S32, S32}, {S32, S64}, {S32, S16}})
461+
.customFor({{S64, S64}});
461462
if (ST.has16BitInsts())
462463
FPToI.legalFor({{S16, S16}});
463464
else
@@ -1161,6 +1162,10 @@ bool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI,
11611162
return legalizeITOFP(MI, MRI, B, true);
11621163
case TargetOpcode::G_UITOFP:
11631164
return legalizeITOFP(MI, MRI, B, false);
1165+
case TargetOpcode::G_FPTOSI:
1166+
return legalizeFPTOI(MI, MRI, B, true);
1167+
case TargetOpcode::G_FPTOUI:
1168+
return legalizeFPTOI(MI, MRI, B, false);
11641169
case TargetOpcode::G_FMINNUM:
11651170
case TargetOpcode::G_FMAXNUM:
11661171
case TargetOpcode::G_FMINNUM_IEEE:
@@ -1522,6 +1527,42 @@ bool AMDGPULegalizerInfo::legalizeITOFP(
15221527
return true;
15231528
}
15241529

1530+
// TODO: Copied from DAG implementation. Verify logic and document how this
1531+
// actually works.
1532+
bool AMDGPULegalizerInfo::legalizeFPTOI(
1533+
MachineInstr &MI, MachineRegisterInfo &MRI,
1534+
MachineIRBuilder &B, bool Signed) const {
1535+
B.setInstr(MI);
1536+
1537+
Register Dst = MI.getOperand(0).getReg();
1538+
Register Src = MI.getOperand(1).getReg();
1539+
1540+
const LLT S64 = LLT::scalar(64);
1541+
const LLT S32 = LLT::scalar(32);
1542+
1543+
assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S64);
1544+
1545+
unsigned Flags = MI.getFlags();
1546+
1547+
auto Trunc = B.buildIntrinsicTrunc(S64, Src, Flags);
1548+
auto K0 = B.buildFConstant(S64, BitsToDouble(UINT64_C(0x3df0000000000000)));
1549+
auto K1 = B.buildFConstant(S64, BitsToDouble(UINT64_C(0xc1f0000000000000)));
1550+
1551+
auto Mul = B.buildFMul(S64, Trunc, K0, Flags);
1552+
auto FloorMul = B.buildFFloor(S64, Mul, Flags);
1553+
auto Fma = B.buildFMA(S64, FloorMul, K1, Trunc, Flags);
1554+
1555+
auto Hi = Signed ?
1556+
B.buildFPTOSI(S32, FloorMul) :
1557+
B.buildFPTOUI(S32, FloorMul);
1558+
auto Lo = B.buildFPTOUI(S32, Fma);
1559+
1560+
B.buildMerge(Dst, { Lo.getReg(0), Hi.getReg(0) });
1561+
MI.eraseFromParent();
1562+
1563+
return true;
1564+
}
1565+
15251566
bool AMDGPULegalizerInfo::legalizeMinNumMaxNum(
15261567
MachineInstr &MI, MachineRegisterInfo &MRI,
15271568
MachineIRBuilder &B) const {

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,6 +50,8 @@ class AMDGPULegalizerInfo : public LegalizerInfo {
5050
MachineIRBuilder &B) const;
5151
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
5252
MachineIRBuilder &B, bool Signed) const;
53+
bool legalizeFPTOI(MachineInstr &MI, MachineRegisterInfo &MRI,
54+
MachineIRBuilder &B, bool Signed) const;
5355
bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
5456
MachineIRBuilder &B) const;
5557
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir

Lines changed: 195 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -159,3 +159,198 @@ body: |
159159
%2:_(s32) = G_ANYEXT %1
160160
$vgpr0 = COPY %2
161161
...
162+
163+
---
164+
name: test_fptosi_s64_s64
165+
body: |
166+
bb.0:
167+
liveins: $vgpr0_vgpr1
168+
169+
; SI-LABEL: name: test_fptosi_s64_s64
170+
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
171+
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
172+
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
173+
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
174+
; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
175+
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
176+
; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
177+
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
178+
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
179+
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
180+
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
181+
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
182+
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
183+
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
184+
; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
185+
; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[XOR]]
186+
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
187+
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
188+
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
189+
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
190+
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
191+
; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
192+
; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
193+
; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
194+
; SI: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C8]]
195+
; SI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
196+
; SI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C9]], [[INTRINSIC_TRUNC]]
197+
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
198+
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)
199+
; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)
200+
; SI: $vgpr0_vgpr1 = COPY [[MV1]](s64)
201+
; VI-LABEL: name: test_fptosi_s64_s64
202+
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
203+
; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[COPY]]
204+
; VI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
205+
; VI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
206+
; VI: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
207+
; VI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
208+
; VI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
209+
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
210+
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)
211+
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)
212+
; VI: $vgpr0_vgpr1 = COPY [[MV]](s64)
213+
%0:_(s64) = COPY $vgpr0_vgpr1
214+
%1:_(s64) = G_FPTOSI %0
215+
$vgpr0_vgpr1 = COPY %1
216+
...
217+
218+
---
219+
name: test_fptosi_s64_s64_flags
220+
body: |
221+
bb.0:
222+
liveins: $vgpr0_vgpr1
223+
224+
; SI-LABEL: name: test_fptosi_s64_s64_flags
225+
; SI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
226+
; SI: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
227+
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
228+
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
229+
; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
230+
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
231+
; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
232+
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
233+
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[C3]]
234+
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
235+
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
236+
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
237+
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
238+
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
239+
; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
240+
; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[XOR]]
241+
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
242+
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
243+
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
244+
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
245+
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[COPY]], [[SELECT]]
246+
; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = nnan G_INTRINSIC_TRUNC [[COPY]]
247+
; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
248+
; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
249+
; SI: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C8]]
250+
; SI: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
251+
; SI: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C9]], [[INTRINSIC_TRUNC]]
252+
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
253+
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)
254+
; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)
255+
; SI: $vgpr0_vgpr1 = COPY [[MV1]](s64)
256+
; VI-LABEL: name: test_fptosi_s64_s64_flags
257+
; VI: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
258+
; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = nnan G_INTRINSIC_TRUNC [[COPY]]
259+
; VI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
260+
; VI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
261+
; VI: [[FMUL:%[0-9]+]]:_(s64) = nnan G_FMUL [[INTRINSIC_TRUNC]], [[C]]
262+
; VI: [[FFLOOR:%[0-9]+]]:_(s64) = nnan G_FFLOOR [[FMUL]]
263+
; VI: [[FMA:%[0-9]+]]:_(s64) = nnan G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
264+
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
265+
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)
266+
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)
267+
; VI: $vgpr0_vgpr1 = COPY [[MV]](s64)
268+
%0:_(s64) = COPY $vgpr0_vgpr1
269+
%1:_(s64) = nnan G_FPTOSI %0
270+
$vgpr0_vgpr1 = COPY %1
271+
...
272+
273+
---
274+
name: test_fptosi_v2s64_to_v2s64
275+
body: |
276+
bb.0:
277+
liveins: $vgpr0_vgpr1_vgpr2_vgpr3
278+
279+
; SI-LABEL: name: test_fptosi_v2s64_to_v2s64
280+
; SI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
281+
; SI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
282+
; SI: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV]](s64)
283+
; SI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
284+
; SI: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 11
285+
; SI: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
286+
; SI: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1023
287+
; SI: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[INT]], [[C2]]
288+
; SI: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 -2147483648
289+
; SI: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV3]], [[C3]]
290+
; SI: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 4503599627370495
291+
; SI: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
292+
; SI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND]](s32)
293+
; SI: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB]](s32)
294+
; SI: [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
295+
; SI: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ASHR]], [[C6]]
296+
; SI: [[AND1:%[0-9]+]]:_(s64) = G_AND [[UV]], [[XOR]]
297+
; SI: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 51
298+
; SI: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB]](s32), [[C5]]
299+
; SI: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB]](s32), [[C7]]
300+
; SI: [[SELECT:%[0-9]+]]:_(s64) = G_SELECT [[ICMP]](s1), [[MV]], [[AND1]]
301+
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP1]](s1), [[UV]], [[SELECT]]
302+
; SI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
303+
; SI: [[C8:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
304+
; SI: [[C9:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
305+
; SI: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C8]]
306+
; SI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
307+
; SI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C9]], [[INTRINSIC_TRUNC]]
308+
; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
309+
; SI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)
310+
; SI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)
311+
; SI: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[UV1]](s64)
312+
; SI: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.ubfe), [[C]](s32), [[C1]](s32)
313+
; SI: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[INT1]], [[C2]]
314+
; SI: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UV5]], [[C3]]
315+
; SI: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[C5]](s32), [[AND2]](s32)
316+
; SI: [[ASHR1:%[0-9]+]]:_(s64) = G_ASHR [[C4]], [[SUB1]](s32)
317+
; SI: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[ASHR1]], [[C6]]
318+
; SI: [[AND3:%[0-9]+]]:_(s64) = G_AND [[UV1]], [[XOR1]]
319+
; SI: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(slt), [[SUB1]](s32), [[C5]]
320+
; SI: [[ICMP3:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[SUB1]](s32), [[C7]]
321+
; SI: [[SELECT1:%[0-9]+]]:_(s64) = G_SELECT [[ICMP2]](s1), [[MV2]], [[AND3]]
322+
; SI: [[SELECT2:%[0-9]+]]:_(s64) = G_SELECT [[ICMP3]](s1), [[UV1]], [[SELECT1]]
323+
; SI: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
324+
; SI: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC1]], [[C8]]
325+
; SI: [[FFLOOR1:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL1]]
326+
; SI: [[FMA1:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR1]], [[C9]], [[INTRINSIC_TRUNC1]]
327+
; SI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR1]](s64)
328+
; SI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA1]](s64)
329+
; SI: [[MV3:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](s32), [[FPTOSI1]](s32)
330+
; SI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV1]](s64), [[MV3]](s64)
331+
; SI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
332+
; VI-LABEL: name: test_fptosi_v2s64_to_v2s64
333+
; VI: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
334+
; VI: [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[COPY]](<2 x s64>)
335+
; VI: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV]]
336+
; VI: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3DF0000000000000
337+
; VI: [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 0xC1F0000000000000
338+
; VI: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC]], [[C]]
339+
; VI: [[FFLOOR:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL]]
340+
; VI: [[FMA:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR]], [[C1]], [[INTRINSIC_TRUNC]]
341+
; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR]](s64)
342+
; VI: [[FPTOUI:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA]](s64)
343+
; VI: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI]](s32), [[FPTOSI]](s32)
344+
; VI: [[INTRINSIC_TRUNC1:%[0-9]+]]:_(s64) = G_INTRINSIC_TRUNC [[UV1]]
345+
; VI: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[INTRINSIC_TRUNC1]], [[C]]
346+
; VI: [[FFLOOR1:%[0-9]+]]:_(s64) = G_FFLOOR [[FMUL1]]
347+
; VI: [[FMA1:%[0-9]+]]:_(s64) = G_FMA [[FFLOOR1]], [[C1]], [[INTRINSIC_TRUNC1]]
348+
; VI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[FFLOOR1]](s64)
349+
; VI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[FMA1]](s64)
350+
; VI: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[FPTOUI1]](s32), [[FPTOSI1]](s32)
351+
; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[MV]](s64), [[MV1]](s64)
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; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
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%0:_(<2 x s64>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%1:_(<2 x s64>) = G_FPTOSI %0
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
356+
...

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