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[GISel] Pass MPO and VA to assignValueToAddress by const reference. NFC (#69810)
Previously they were passed by non-const reference. No in tree target modifies the values. This makes it possible to call assignValueToAddress from assignCustomValue without a const_cast. For example in this patch #69138.
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12 files changed

+64
-49
lines changed

12 files changed

+64
-49
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -274,16 +274,16 @@ class CallLowering {
274274
/// location. Load or store it there, with appropriate extension
275275
/// if necessary.
276276
virtual void assignValueToAddress(Register ValVReg, Register Addr,
277-
LLT MemTy, MachinePointerInfo &MPO,
278-
CCValAssign &VA) = 0;
277+
LLT MemTy, const MachinePointerInfo &MPO,
278+
const CCValAssign &VA) = 0;
279279

280280
/// An overload which takes an ArgInfo if additional information about the
281281
/// arg is needed. \p ValRegIndex is the index in \p Arg.Regs for the value
282282
/// to store.
283283
virtual void assignValueToAddress(const ArgInfo &Arg, unsigned ValRegIndex,
284284
Register Addr, LLT MemTy,
285-
MachinePointerInfo &MPO,
286-
CCValAssign &VA) {
285+
const MachinePointerInfo &MPO,
286+
const CCValAssign &VA) {
287287
assignValueToAddress(Arg.Regs[ValRegIndex], Addr, MemTy, MPO, VA);
288288
}
289289

@@ -311,7 +311,7 @@ class CallLowering {
311311

312312
/// Extend a register to the location type given in VA, capped at extending
313313
/// to at most MaxSize bits. If MaxSizeBits is 0 then no maximum is set.
314-
Register extendRegister(Register ValReg, CCValAssign &VA,
314+
Register extendRegister(Register ValReg, const CCValAssign &VA,
315315
unsigned MaxSizeBits = 0);
316316
};
317317

‎llvm/lib/CodeGen/GlobalISel/CallLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1135,7 +1135,7 @@ void CallLowering::ValueHandler::copyArgumentMemory(
11351135
}
11361136

11371137
Register CallLowering::ValueHandler::extendRegister(Register ValReg,
1138-
CCValAssign &VA,
1138+
const CCValAssign &VA,
11391139
unsigned MaxSizeBits) {
11401140
LLT LocTy{VA.getLocVT()};
11411141
LLT ValTy{VA.getValVT()};

‎llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,8 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler {
164164
}
165165

166166
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
167-
MachinePointerInfo &MPO, CCValAssign &VA) override {
167+
const MachinePointerInfo &MPO,
168+
const CCValAssign &VA) override {
168169
MachineFunction &MF = MIRBuilder.getMF();
169170

170171
LLT ValTy(VA.getValVT());
@@ -290,16 +291,18 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
290291
}
291292

292293
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
293-
MachinePointerInfo &MPO, CCValAssign &VA) override {
294+
const MachinePointerInfo &MPO,
295+
const CCValAssign &VA) override {
294296
MachineFunction &MF = MIRBuilder.getMF();
295297
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOStore, MemTy,
296298
inferAlignFromPtrInfo(MF, MPO));
297299
MIRBuilder.buildStore(ValVReg, Addr, *MMO);
298300
}
299301

300302
void assignValueToAddress(const CallLowering::ArgInfo &Arg, unsigned RegIndex,
301-
Register Addr, LLT MemTy, MachinePointerInfo &MPO,
302-
CCValAssign &VA) override {
303+
Register Addr, LLT MemTy,
304+
const MachinePointerInfo &MPO,
305+
const CCValAssign &VA) override {
303306
unsigned MaxSize = MemTy.getSizeInBytes() * 8;
304307
// For varargs, we always want to extend them to 8 bytes, in which case
305308
// we disable setting a max.

‎llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,7 @@ namespace {
3232

3333
/// Wrapper around extendRegister to ensure we extend to a full 32-bit register.
3434
static Register extendRegisterMin32(CallLowering::ValueHandler &Handler,
35-
Register ValVReg, CCValAssign &VA) {
35+
Register ValVReg, const CCValAssign &VA) {
3636
if (VA.getLocVT().getSizeInBits() < 32) {
3737
// 16-bit types are reported as legal for 32-bit registers. We need to
3838
// extend and do a 32-bit copy to avoid the verifier complaining about it.
@@ -56,7 +56,8 @@ struct AMDGPUOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
5656
}
5757

5858
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
59-
MachinePointerInfo &MPO, CCValAssign &VA) override {
59+
const MachinePointerInfo &MPO,
60+
const CCValAssign &VA) override {
6061
llvm_unreachable("not implemented");
6162
}
6263

@@ -137,7 +138,8 @@ struct AMDGPUIncomingArgHandler : public CallLowering::IncomingValueHandler {
137138
}
138139

139140
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
140-
MachinePointerInfo &MPO, CCValAssign &VA) override {
141+
const MachinePointerInfo &MPO,
142+
const CCValAssign &VA) override {
141143
MachineFunction &MF = MIRBuilder.getMF();
142144

143145
auto MMO = MF.getMachineMemOperand(
@@ -236,7 +238,8 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
236238
}
237239

238240
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
239-
MachinePointerInfo &MPO, CCValAssign &VA) override {
241+
const MachinePointerInfo &MPO,
242+
const CCValAssign &VA) override {
240243
MachineFunction &MF = MIRBuilder.getMF();
241244
uint64_t LocMemOffset = VA.getLocMemOffset();
242245
const auto &ST = MF.getSubtarget<GCNSubtarget>();
@@ -249,7 +252,8 @@ struct AMDGPUOutgoingArgHandler : public AMDGPUOutgoingValueHandler {
249252

250253
void assignValueToAddress(const CallLowering::ArgInfo &Arg,
251254
unsigned ValRegIndex, Register Addr, LLT MemTy,
252-
MachinePointerInfo &MPO, CCValAssign &VA) override {
255+
const MachinePointerInfo &MPO,
256+
const CCValAssign &VA) override {
253257
Register ValVReg = VA.getLocInfo() != CCValAssign::LocInfo::FPExt
254258
? extendRegister(Arg.Regs[ValRegIndex], VA)
255259
: Arg.Regs[ValRegIndex];

‎llvm/lib/Target/ARM/ARMCallLowering.cpp

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,8 @@ struct ARMOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
123123
}
124124

125125
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
126-
MachinePointerInfo &MPO, CCValAssign &VA) override {
126+
const MachinePointerInfo &MPO,
127+
const CCValAssign &VA) override {
127128
Register ExtReg = extendRegister(ValVReg, VA);
128129
auto MMO = MIRBuilder.getMF().getMachineMemOperand(
129130
MPO, MachineMemOperand::MOStore, MemTy, Align(1));
@@ -255,7 +256,8 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
255256
}
256257

257258
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
258-
MachinePointerInfo &MPO, CCValAssign &VA) override {
259+
const MachinePointerInfo &MPO,
260+
const CCValAssign &VA) override {
259261
if (VA.getLocInfo() == CCValAssign::SExt ||
260262
VA.getLocInfo() == CCValAssign::ZExt) {
261263
// If the value is zero- or sign-extended, its size becomes 4 bytes, so
@@ -272,7 +274,7 @@ struct ARMIncomingValueHandler : public CallLowering::IncomingValueHandler {
272274
}
273275

274276
MachineInstrBuilder buildLoad(const DstOp &Res, Register Addr, LLT MemTy,
275-
MachinePointerInfo &MPO) {
277+
const MachinePointerInfo &MPO) {
276278
MachineFunction &MF = MIRBuilder.getMF();
277279

278280
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,

‎llvm/lib/Target/M68k/GISel/M68kCallLowering.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -43,7 +43,8 @@ struct M68kOutgoingArgHandler : public CallLowering::OutgoingValueHandler {
4343
}
4444

4545
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
46-
MachinePointerInfo &MPO, CCValAssign &VA) override {
46+
const MachinePointerInfo &MPO,
47+
const CCValAssign &VA) override {
4748
MachineFunction &MF = MIRBuilder.getMF();
4849
Register ExtReg = extendRegister(ValVReg, VA);
4950

@@ -132,11 +133,9 @@ void M68kIncomingValueHandler::assignValueToReg(Register ValVReg,
132133
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
133134
}
134135

135-
void M68kIncomingValueHandler::assignValueToAddress(Register ValVReg,
136-
Register Addr,
137-
LLT MemTy,
138-
MachinePointerInfo &MPO,
139-
CCValAssign &VA) {
136+
void M68kIncomingValueHandler::assignValueToAddress(
137+
Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
138+
const CCValAssign &VA) {
140139
MachineFunction &MF = MIRBuilder.getMF();
141140
auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
142141
inferAlignFromPtrInfo(MF, MPO));

‎llvm/lib/Target/M68k/GISel/M68kCallLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,8 @@ struct M68kIncomingValueHandler : public CallLowering::IncomingValueHandler {
5656
CCValAssign VA) override;
5757

5858
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
59-
MachinePointerInfo &MPO, CCValAssign &VA) override;
59+
const MachinePointerInfo &MPO,
60+
const CCValAssign &VA) override;
6061

6162
Register getStackAddress(uint64_t Size, int64_t Offset,
6263
MachinePointerInfo &MPO,

‎llvm/lib/Target/Mips/MipsCallLowering.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,8 @@ class MipsIncomingValueHandler : public CallLowering::IncomingValueHandler {
9999
MachinePointerInfo &MPO,
100100
ISD::ArgFlagsTy Flags) override;
101101
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
102-
MachinePointerInfo &MPO, CCValAssign &VA) override;
102+
const MachinePointerInfo &MPO,
103+
const CCValAssign &VA) override;
103104

104105
unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
105106
ArrayRef<CCValAssign> VAs,
@@ -149,10 +150,9 @@ Register MipsIncomingValueHandler::getStackAddress(uint64_t Size,
149150
return MIRBuilder.buildFrameIndex(LLT::pointer(0, 32), FI).getReg(0);
150151
}
151152

152-
void MipsIncomingValueHandler::assignValueToAddress(Register ValVReg,
153-
Register Addr, LLT MemTy,
154-
MachinePointerInfo &MPO,
155-
CCValAssign &VA) {
153+
void MipsIncomingValueHandler::assignValueToAddress(
154+
Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
155+
const CCValAssign &VA) {
156156
MachineFunction &MF = MIRBuilder.getMF();
157157
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
158158
inferAlignFromPtrInfo(MF, MPO));
@@ -207,7 +207,8 @@ class MipsOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
207207
ISD::ArgFlagsTy Flags) override;
208208

209209
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
210-
MachinePointerInfo &MPO, CCValAssign &VA) override;
210+
const MachinePointerInfo &MPO,
211+
const CCValAssign &VA) override;
211212
unsigned assignCustomValue(CallLowering::ArgInfo &Arg,
212213
ArrayRef<CCValAssign> VAs,
213214
std::function<void()> *Thunk) override;
@@ -240,10 +241,9 @@ Register MipsOutgoingValueHandler::getStackAddress(uint64_t Size,
240241
return AddrReg.getReg(0);
241242
}
242243

243-
void MipsOutgoingValueHandler::assignValueToAddress(Register ValVReg,
244-
Register Addr, LLT MemTy,
245-
MachinePointerInfo &MPO,
246-
CCValAssign &VA) {
244+
void MipsOutgoingValueHandler::assignValueToAddress(
245+
Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
246+
const CCValAssign &VA) {
247247
MachineFunction &MF = MIRBuilder.getMF();
248248
uint64_t LocMemOffset = VA.getLocMemOffset();
249249

‎llvm/lib/Target/PowerPC/GISel/PPCCallLowering.cpp

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -38,7 +38,8 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
3838
void assignValueToReg(Register ValVReg, Register PhysReg,
3939
CCValAssign VA) override;
4040
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
41-
MachinePointerInfo &MPO, CCValAssign &VA) override;
41+
const MachinePointerInfo &MPO,
42+
const CCValAssign &VA) override;
4243
Register getStackAddress(uint64_t Size, int64_t Offset,
4344
MachinePointerInfo &MPO,
4445
ISD::ArgFlagsTy Flags) override;
@@ -56,8 +57,8 @@ void OutgoingArgHandler::assignValueToReg(Register ValVReg, Register PhysReg,
5657

5758
void OutgoingArgHandler::assignValueToAddress(Register ValVReg, Register Addr,
5859
LLT MemTy,
59-
MachinePointerInfo &MPO,
60-
CCValAssign &VA) {
60+
const MachinePointerInfo &MPO,
61+
const CCValAssign &VA) {
6162
llvm_unreachable("unimplemented");
6263
}
6364

@@ -148,13 +149,13 @@ void PPCIncomingValueHandler::assignValueToReg(Register ValVReg,
148149
IncomingValueHandler::assignValueToReg(ValVReg, PhysReg, VA);
149150
}
150151

151-
void PPCIncomingValueHandler::assignValueToAddress(Register ValVReg,
152-
Register Addr, LLT MemTy,
153-
MachinePointerInfo &MPO,
154-
CCValAssign &VA) {
152+
void PPCIncomingValueHandler::assignValueToAddress(
153+
Register ValVReg, Register Addr, LLT MemTy, const MachinePointerInfo &MPO,
154+
const CCValAssign &VA) {
155155
// define a lambda expression to load value
156-
auto BuildLoad = [](MachineIRBuilder &MIRBuilder, MachinePointerInfo &MPO,
157-
LLT MemTy, const DstOp &Res, Register Addr) {
156+
auto BuildLoad = [](MachineIRBuilder &MIRBuilder,
157+
const MachinePointerInfo &MPO, LLT MemTy,
158+
const DstOp &Res, Register Addr) {
158159
MachineFunction &MF = MIRBuilder.getMF();
159160
auto *MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
160161
inferAlignFromPtrInfo(MF, MPO));

‎llvm/lib/Target/PowerPC/GISel/PPCCallLowering.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,8 @@ class PPCIncomingValueHandler : public CallLowering::IncomingValueHandler {
4949
CCValAssign VA) override;
5050

5151
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
52-
MachinePointerInfo &MPO, CCValAssign &VA) override;
52+
const MachinePointerInfo &MPO,
53+
const CCValAssign &VA) override;
5354

5455
Register getStackAddress(uint64_t Size, int64_t Offset,
5556
MachinePointerInfo &MPO,

‎llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,8 @@ struct RISCVOutgoingValueHandler : public CallLowering::OutgoingValueHandler {
7878
}
7979

8080
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
81-
MachinePointerInfo &MPO, CCValAssign &VA) override {
81+
const MachinePointerInfo &MPO,
82+
const CCValAssign &VA) override {
8283
MachineFunction &MF = MIRBuilder.getMF();
8384
uint64_t LocMemOffset = VA.getLocMemOffset();
8485

@@ -155,7 +156,8 @@ struct RISCVIncomingValueHandler : public CallLowering::IncomingValueHandler {
155156
}
156157

157158
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
158-
MachinePointerInfo &MPO, CCValAssign &VA) override {
159+
const MachinePointerInfo &MPO,
160+
const CCValAssign &VA) override {
159161
MachineFunction &MF = MIRBuilder.getMF();
160162
auto MMO = MF.getMachineMemOperand(MPO, MachineMemOperand::MOLoad, MemTy,
161163
inferAlignFromPtrInfo(MF, MPO));

‎llvm/lib/Target/X86/GISel/X86CallLowering.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -113,7 +113,8 @@ struct X86OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
113113
}
114114

115115
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
116-
MachinePointerInfo &MPO, CCValAssign &VA) override {
116+
const MachinePointerInfo &MPO,
117+
const CCValAssign &VA) override {
117118
MachineFunction &MF = MIRBuilder.getMF();
118119
Register ExtReg = extendRegister(ValVReg, VA);
119120

@@ -201,7 +202,8 @@ struct X86IncomingValueHandler : public CallLowering::IncomingValueHandler {
201202
}
202203

203204
void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
204-
MachinePointerInfo &MPO, CCValAssign &VA) override {
205+
const MachinePointerInfo &MPO,
206+
const CCValAssign &VA) override {
205207
MachineFunction &MF = MIRBuilder.getMF();
206208
auto *MMO = MF.getMachineMemOperand(
207209
MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, MemTy,

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