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[X86] Add test case for PR46455.
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llvm/lib/Target/X86/X86ISelLowering.cpp

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@@ -44523,6 +44523,8 @@ static SDValue combineFaddFsub(SDNode *N, SelectionDAG &DAG,
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isHorizontalBinOp(LHS, RHS, DAG, Subtarget, IsFadd))
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return DAG.getNode(HorizOpcode, SDLoc(N), VT, LHS, RHS);
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// NOTE: isHorizontalBinOp may have changed LHS/RHS variables.
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return SDValue();
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}
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llvm/test/CodeGen/X86/pr46455.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=avx512vl,avx512bw,avx512dq | FileCheck %s
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define void @EntryModule(i8** %buffer_table) {
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; CHECK-LABEL: EntryModule:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vxorps %xmm0, %xmm0, %xmm0
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; CHECK-NEXT: movq (%rdi), %rax
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; CHECK-NEXT: movq 24(%rdi), %rcx
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; CHECK-NEXT: vcmpneqps (%rax), %ymm0, %ymm0
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; CHECK-NEXT: vandps {{.*}}(%rip){1to4}, %xmm0, %xmm1
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; CHECK-NEXT: vpermilps {{.*#+}} xmm2 = xmm1[2,3,0,1]
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; CHECK-NEXT: vpermilps {{.*#+}} xmm3 = xmm1[3,1,2,3]
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; CHECK-NEXT: vpaddd %xmm3, %xmm2, %xmm2
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; CHECK-NEXT: vpsubd %xmm0, %xmm1, %xmm0
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; CHECK-NEXT: vpaddd %xmm2, %xmm0, %xmm0
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; CHECK-NEXT: vmovd %xmm0, (%rcx)
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; CHECK-NEXT: vzeroupper
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; CHECK-NEXT: retq
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entry:
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%i = bitcast i8** %buffer_table to <8 x float>**
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%i1 = load <8 x float>*, <8 x float>** %i, align 8
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%i6 = load <8 x float>, <8 x float>* %i1, align 16
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%i7 = fcmp une <8 x float> %i6, zeroinitializer
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%i8 = zext <8 x i1> %i7 to <8 x i32>
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%i18 = getelementptr inbounds i8*, i8** %buffer_table, i64 3
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%i19 = load i8*, i8** %i18, align 8
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%shift = shufflevector <8 x i32> %i8, <8 x i32> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%i20 = add nuw nsw <8 x i32> %shift, %i8
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%shift13 = shufflevector <8 x i32> %i8, <8 x i32> undef, <8 x i32> <i32 2, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%i21 = add nuw nsw <8 x i32> %i20, %shift13
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%shift14 = shufflevector <8 x i32> %i8, <8 x i32> undef, <8 x i32> <i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
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%i22 = add nuw nsw <8 x i32> %i21, %shift14
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%i23 = extractelement <8 x i32> %i22, i32 0
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%i24 = bitcast i8* %i19 to i32*
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store i32 %i23, i32* %i24, align 8
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ret void
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}

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