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[RISCV] Re-generate test checks so we pick up implicit on whole register moves. NFC
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‎llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ body: |
1313
; CHECK-NEXT: {{ $}}
1414
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
1515
; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
16-
; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2
16+
; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2, implicit $vtype
1717
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
1818
$v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
1919
$v12m2 = COPY $v28m2
@@ -61,7 +61,7 @@ body: |
6161
; CHECK-NEXT: {{ $}}
6262
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
6363
; CHECK-NEXT: $v28m4 = VL4RE32_V $x16
64-
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4
64+
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype
6565
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
6666
$v28m4 = VL4RE32_V $x16
6767
$v12m4 = COPY $v28m4
@@ -78,7 +78,7 @@ body: |
7878
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
7979
; CHECK-NEXT: $v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
8080
; CHECK-NEXT: $v4m4, $x0 = PseudoVLE32FF_V_M4 undef $v4m4, $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit-def $vl
81-
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4
81+
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype
8282
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
8383
$v28m4 = PseudoVMV_V_I_M4 undef $v28m4, 0, $noreg, 5, 0, implicit $vl, implicit $vtype
8484
$v4m4,$x0 = PseudoVLE32FF_V_M4 undef $v4m4, $x16, $noreg, 5, 0, implicit-def $vl
@@ -99,7 +99,7 @@ body: |
9999
; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
100100
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
101101
; CHECK-NEXT: $v4m4 = PseudoVLE32_V_M4 undef $v4m4, killed $x18, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
102-
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4
102+
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype
103103
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
104104
$v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
105105
$x15 = PseudoVSETVLI $x17, 73, implicit-def $vl, implicit-def $vtype
@@ -145,7 +145,7 @@ body: |
145145
; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
146146
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
147147
; CHECK-NEXT: $v0m2 = PseudoVLE32_V_M2 undef $v0m2, $x18, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
148-
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4
148+
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype
149149
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
150150
$v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
151151
$x0 = PseudoVSETVLIX0 $x0, 73, implicit-def $vl, implicit-def $vtype
@@ -165,7 +165,7 @@ body: |
165165
; CHECK-NEXT: $v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
166166
; CHECK-NEXT: $v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
167167
; CHECK-NEXT: early-clobber $v28m4 = PseudoVWADD_VV_M2 undef $v28m4, $v26m2, $v8m2, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
168-
; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2
168+
; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2, implicit $vtype
169169
$x15 = PseudoVSETIVLI 4, 73, implicit-def $vl, implicit-def $vtype
170170
$v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg, 4, 0, implicit $vl, implicit $vtype
171171
$v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg, 4, 0, implicit $vl, implicit $vtype
@@ -185,7 +185,7 @@ body: |
185185
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 82 /* e32, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
186186
; CHECK-NEXT: $v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
187187
; CHECK-NEXT: $x0 = PseudoVSETVLIX0 $x0, 74 /* e16, m4, ta, mu */, implicit-def $vl, implicit-def $vtype
188-
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4
188+
; CHECK-NEXT: $v12m4 = VMV4R_V $v28m4, implicit $vtype
189189
$x15 = PseudoVSETVLI $x14, 82, implicit-def $vl, implicit-def $vtype
190190
$v28m4 = PseudoVLE32_V_M4 undef $v28m4, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
191191
$x0 = PseudoVSETVLIX0 $x0, 74, implicit-def $vl, implicit-def $vtype
@@ -202,7 +202,7 @@ body: |
202202
; CHECK-NEXT: {{ $}}
203203
; CHECK-NEXT: $x11 = PseudoVSETIVLI 1, 64 /* e8, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
204204
; CHECK-NEXT: $v8 = PseudoVWREDSUM_VS_M1_E8 killed renamable $v8, killed renamable $v26, killed renamable $v27, 1, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
205-
; CHECK-NEXT: $v26 = VMV1R_V killed $v8
205+
; CHECK-NEXT: $v26 = VMV1R_V killed $v8, implicit $vtype
206206
; CHECK-NEXT: $x10 = PseudoVSETVLI killed renamable $x10, 75 /* e16, m8, ta, mu */, implicit-def $vl, implicit-def $vtype
207207
; CHECK-NEXT: $v8m8 = VL8RE8_V killed $x10
208208
$x11 = PseudoVSETIVLI 1, 64, implicit-def $vl, implicit-def $vtype
@@ -222,7 +222,7 @@ body: |
222222
; CHECK-NEXT: {{ $}}
223223
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
224224
; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
225-
; CHECK-NEXT: $v10 = VMV1R_V $v8
225+
; CHECK-NEXT: $v10 = VMV1R_V $v8, implicit $vtype
226226
$x15 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype
227227
$v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
228228
$v10 = COPY $v8
@@ -238,7 +238,7 @@ body: |
238238
; CHECK-NEXT: {{ $}}
239239
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
240240
; CHECK-NEXT: $v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
241-
; CHECK-NEXT: $v10m2 = VMV2R_V $v8m2
241+
; CHECK-NEXT: $v10m2 = VMV2R_V $v8m2, implicit $vtype
242242
$x15 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype
243243
$v8_v9 = PseudoVLSEG2E32_V_M1 undef $v8_v9, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
244244
$v10_v11 = COPY $v8_v9
@@ -254,7 +254,7 @@ body: |
254254
; CHECK-NEXT: {{ $}}
255255
; CHECK-NEXT: $x15 = PseudoVSETVLI $x14, 87 /* e32, mf2, ta, mu */, implicit-def $vl, implicit-def $vtype
256256
; CHECK-NEXT: $v28 = PseudoVLE32_V_MF2 undef $v28, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
257-
; CHECK-NEXT: $v12 = VMV1R_V $v28
257+
; CHECK-NEXT: $v12 = VMV1R_V $v28, implicit $vtype
258258
$x15 = PseudoVSETVLI $x14, 87, implicit-def $vl, implicit-def $vtype
259259
$v28 = PseudoVLE32_V_MF2 undef $v28, killed $x16, $noreg, 5, 0, implicit $vl, implicit $vtype
260260
$v12 = COPY $v28
@@ -272,7 +272,7 @@ body: |
272272
; CHECK-NEXT: $v8_v9_v10_v11_v12_v13_v14_v15 = PseudoVLSEG8E32_V_M1 undef $v8_v9_v10_v11_v12_v13_v14_v15, killed $x12, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
273273
; CHECK-NEXT: $x0 = PseudoVSETIVLI 10, 80 /* e32, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
274274
; CHECK-NEXT: $v15 = PseudoVLE32_V_M1 undef $v15, killed $x16, $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit killed $v8_v9_v10_v11_v12_v13_v14_v15, implicit-def $v8_v9_v10_v11_v12_v13_v14_v15
275-
; CHECK-NEXT: $v24m8 = VMV8R_V killed $v8m8
275+
; CHECK-NEXT: $v24m8 = VMV8R_V killed $v8m8, implicit $vtype
276276
$x0 = PseudoVSETVLI $x14, 80, implicit-def $vl, implicit-def $vtype
277277
$v8_v9_v10_v11_v12_v13_v14_v15 = PseudoVLSEG8E32_V_M1 undef $v8_v9_v10_v11_v12_v13_v14_v15, killed $x12, $noreg, 5, 0, implicit $vl, implicit $vtype
278278
$x0 = PseudoVSETIVLI 10, 80, implicit-def $vl, implicit-def $vtype
@@ -290,9 +290,9 @@ body: |
290290
; CHECK-NEXT: {{ $}}
291291
; CHECK-NEXT: $x0 = PseudoVSETVLI $x10, 201 /* e16, m2, ta, ma */, implicit-def $vl, implicit-def $vtype
292292
; CHECK-NEXT: $v10m2 = PseudoVLE16_V_M2 undef $v10m2, killed $x11, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
293-
; CHECK-NEXT: $v10 = VMV1R_V $v8
294-
; CHECK-NEXT: $v11 = VMV1R_V $v9
295-
; CHECK-NEXT: $v12m2 = VMV2R_V $v10m2
293+
; CHECK-NEXT: $v10 = VMV1R_V $v8, implicit $vtype
294+
; CHECK-NEXT: $v11 = VMV1R_V $v9, implicit $vtype
295+
; CHECK-NEXT: $v12m2 = VMV2R_V $v10m2, implicit $vtype
296296
$x0 = PseudoVSETVLI $x10, 201, implicit-def $vl, implicit-def $vtype
297297
$v10m2 = PseudoVLE16_V_M2 undef $v10m2, killed $x11, $noreg, 4, 0, implicit $vl, implicit $vtype
298298
$v10 = COPY $v8

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