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[SDAG] Use BatchAAResults for querying alias analysis (AA) results (#123934)
Once we get to SelectionDAG the IR should not be changing anymore, so we can use BatchAAResults rather than AAResults to cache AA queries. This should be a NFC change for targets that enable AA during codegen (such as AArch64), but also give a nice compile-time improvement in some cases. See: #123787 (comment) Note: This follows Nikita's suggestion on #123787.
1 parent 4b0df28 commit 7781381

18 files changed

+112
-76
lines changed

‎llvm/include/llvm/Analysis/AliasAnalysis.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -643,6 +643,9 @@ class BatchAAResults {
643643
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal = false) {
644644
return isNoModRef(AA.getModRefInfoMask(Loc, AAQI, OrLocal));
645645
}
646+
bool pointsToConstantMemory(const Value *P, bool OrLocal = false) {
647+
return pointsToConstantMemory(MemoryLocation::getBeforeOrAfter(P), OrLocal);
648+
}
646649
ModRefInfo getModRefInfoMask(const MemoryLocation &Loc,
647650
bool IgnoreLocals = false) {
648651
return AA.getModRefInfoMask(Loc, AAQI, IgnoreLocals);
@@ -668,6 +671,9 @@ class BatchAAResults {
668671
MemoryLocation(V2, LocationSize::precise(1))) ==
669672
AliasResult::MustAlias;
670673
}
674+
bool isNoAlias(const MemoryLocation &LocA, const MemoryLocation &LocB) {
675+
return alias(LocA, LocB) == AliasResult::NoAlias;
676+
}
671677
ModRefInfo callCapturesBefore(const Instruction *I,
672678
const MemoryLocation &MemLoc,
673679
DominatorTree *DT) {

‎llvm/include/llvm/CodeGen/MachineInstr.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ class DILabel;
4242
class Instruction;
4343
class MDNode;
4444
class AAResults;
45+
class BatchAAResults;
4546
template <typename T> class ArrayRef;
4647
class DIExpression;
4748
class DILocalVariable;
@@ -1753,6 +1754,8 @@ class MachineInstr
17531754
/// @param AA Optional alias analysis, used to compare memory operands.
17541755
/// @param Other MachineInstr to check aliasing against.
17551756
/// @param UseTBAA Whether to pass TBAA information to alias analysis.
1757+
bool mayAlias(BatchAAResults *AA, const MachineInstr &Other,
1758+
bool UseTBAA) const;
17561759
bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const;
17571760

17581761
/// Return true if this instruction may have an ordered

‎llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#include "llvm/ADT/SmallVector.h"
2020
#include "llvm/ADT/SparseMultiSet.h"
2121
#include "llvm/ADT/identity.h"
22+
#include "llvm/Analysis/AliasAnalysis.h"
2223
#include "llvm/CodeGen/LiveRegUnits.h"
2324
#include "llvm/CodeGen/MachineBasicBlock.h"
2425
#include "llvm/CodeGen/ScheduleDAG.h"
@@ -169,7 +170,7 @@ namespace llvm {
169170
/// Tracks the last instructions in this region using each virtual register.
170171
VReg2SUnitOperIdxMultiMap CurrentVRegUses;
171172

172-
AAResults *AAForDep = nullptr;
173+
mutable std::optional<BatchAAResults> AAForDep;
173174

174175
/// Remember a generic side-effecting instruction as we proceed.
175176
/// No other SU ever gets scheduled around it (except in the special
@@ -201,6 +202,13 @@ namespace llvm {
201202
/// a means of remembering which SUs depend on which memory locations.
202203
class Value2SUsMap;
203204

205+
/// Returns a (possibly null) pointer to the current BatchAAResults.
206+
BatchAAResults *getAAForDep() const {
207+
if (AAForDep.has_value())
208+
return &AAForDep.value();
209+
return nullptr;
210+
}
211+
204212
/// Reduces maps in FIFO order, by N SUs. This is better than turning
205213
/// every Nth memory SU into BarrierChain in buildSchedGraph(), since
206214
/// it avoids unnecessary edges between seen SUs above the new BarrierChain,

‎llvm/include/llvm/CodeGen/SelectionDAG.h

Lines changed: 12 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ class Type;
6161
template <class GraphType> struct GraphTraits;
6262
template <typename T, unsigned int N> class SmallSetVector;
6363
template <typename T, typename Enable> struct FoldingSetTrait;
64-
class AAResults;
64+
class BatchAAResults;
6565
class BlockAddress;
6666
class BlockFrequencyInfo;
6767
class Constant;
@@ -602,7 +602,8 @@ class SelectionDAG {
602602
/// certain types of nodes together, or eliminating superfluous nodes. The
603603
/// Level argument controls whether Combine is allowed to produce nodes and
604604
/// types that are illegal on the target.
605-
void Combine(CombineLevel Level, AAResults *AA, CodeGenOptLevel OptLevel);
605+
void Combine(CombineLevel Level, BatchAAResults *BatchAA,
606+
CodeGenOptLevel OptLevel);
606607

607608
/// This transforms the SelectionDAG into a SelectionDAG that
608609
/// only uses types natively supported by the target.
@@ -1202,12 +1203,14 @@ class SelectionDAG {
12021203
/* \p CI if not null is the memset call being lowered.
12031204
* \p OverrideTailCall is an optional parameter that can be used to override
12041205
* the tail call optimization decision. */
1205-
SDValue
1206-
getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
1207-
SDValue Size, Align Alignment, bool isVol, bool AlwaysInline,
1208-
const CallInst *CI, std::optional<bool> OverrideTailCall,
1209-
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo,
1210-
const AAMDNodes &AAInfo = AAMDNodes(), AAResults *AA = nullptr);
1206+
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
1207+
SDValue Size, Align Alignment, bool isVol,
1208+
bool AlwaysInline, const CallInst *CI,
1209+
std::optional<bool> OverrideTailCall,
1210+
MachinePointerInfo DstPtrInfo,
1211+
MachinePointerInfo SrcPtrInfo,
1212+
const AAMDNodes &AAInfo = AAMDNodes(),
1213+
BatchAAResults *BatchAA = nullptr);
12111214

12121215
/* \p CI if not null is the memset call being lowered.
12131216
* \p OverrideTailCall is an optional parameter that can be used to override
@@ -1218,7 +1221,7 @@ class SelectionDAG {
12181221
MachinePointerInfo DstPtrInfo,
12191222
MachinePointerInfo SrcPtrInfo,
12201223
const AAMDNodes &AAInfo = AAMDNodes(),
1221-
AAResults *AA = nullptr);
1224+
BatchAAResults *BatchAA = nullptr);
12221225

12231226
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src,
12241227
SDValue Size, Align Alignment, bool isVol,

‎llvm/include/llvm/CodeGen/SelectionDAGISel.h

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@
1414
#ifndef LLVM_CODEGEN_SELECTIONDAGISEL_H
1515
#define LLVM_CODEGEN_SELECTIONDAGISEL_H
1616

17+
#include "llvm/Analysis/AliasAnalysis.h"
1718
#include "llvm/CodeGen/MachineFunctionPass.h"
1819
#include "llvm/CodeGen/MachinePassManager.h"
1920
#include "llvm/CodeGen/SelectionDAG.h"
@@ -52,7 +53,7 @@ class SelectionDAGISel {
5253
MachineRegisterInfo *RegInfo;
5354
SelectionDAG *CurDAG;
5455
std::unique_ptr<SelectionDAGBuilder> SDB;
55-
AAResults *AA = nullptr;
56+
mutable std::optional<BatchAAResults> BatchAA;
5657
AssumptionCache *AC = nullptr;
5758
GCFunctionInfo *GFI = nullptr;
5859
SSPLayoutInfo *SP = nullptr;
@@ -81,6 +82,13 @@ class SelectionDAGISel {
8182
CodeGenOptLevel OL = CodeGenOptLevel::Default);
8283
virtual ~SelectionDAGISel();
8384

85+
/// Returns a (possibly null) pointer to the current BatchAAResults.
86+
BatchAAResults *getBatchAA() const {
87+
if (BatchAA.has_value())
88+
return &BatchAA.value();
89+
return nullptr;
90+
}
91+
8492
const TargetLowering *getTargetLowering() const { return TLI; }
8593

8694
void initializeAnalysisResults(MachineFunctionAnalysisManager &MFAM);

‎llvm/lib/CodeGen/MachineInstr.cpp

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1350,8 +1350,9 @@ bool MachineInstr::wouldBeTriviallyDead() const {
13501350
return isPHI() || isSafeToMove(SawStore);
13511351
}
13521352

1353-
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
1354-
bool UseTBAA, const MachineMemOperand *MMOa,
1353+
static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI,
1354+
BatchAAResults *AA, bool UseTBAA,
1355+
const MachineMemOperand *MMOa,
13551356
const MachineMemOperand *MMOb) {
13561357
// The following interface to AA is fashioned after DAGCombiner::isAlias and
13571358
// operates with MachineMemOperand offset with some important assumptions:
@@ -1434,7 +1435,7 @@ static bool MemOperandsHaveAlias(const MachineFrameInfo &MFI, AAResults *AA,
14341435
MemoryLocation(ValB, LocB, UseTBAA ? MMOb->getAAInfo() : AAMDNodes()));
14351436
}
14361437

1437-
bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1438+
bool MachineInstr::mayAlias(BatchAAResults *AA, const MachineInstr &Other,
14381439
bool UseTBAA) const {
14391440
const MachineFunction *MF = getMF();
14401441
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
@@ -1478,6 +1479,15 @@ bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
14781479
return false;
14791480
}
14801481

1482+
bool MachineInstr::mayAlias(AAResults *AA, const MachineInstr &Other,
1483+
bool UseTBAA) const {
1484+
if (AA) {
1485+
BatchAAResults BAA(*AA);
1486+
return mayAlias(&BAA, Other, UseTBAA);
1487+
}
1488+
return mayAlias(static_cast<BatchAAResults *>(nullptr), Other, UseTBAA);
1489+
}
1490+
14811491
/// hasOrderedMemoryRef - Return true if this instruction may have an ordered
14821492
/// or volatile memory reference, or if the information describing the memory
14831493
/// reference is not available. Return false if it is known to have no ordered

‎llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -551,7 +551,7 @@ void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
551551

552552
void ScheduleDAGInstrs::addChainDependency (SUnit *SUa, SUnit *SUb,
553553
unsigned Latency) {
554-
if (SUa->getInstr()->mayAlias(AAForDep, *SUb->getInstr(), UseTBAA)) {
554+
if (SUa->getInstr()->mayAlias(getAAForDep(), *SUb->getInstr(), UseTBAA)) {
555555
SDep Dep(SUa, SDep::MayAliasMem);
556556
Dep.setLatency(Latency);
557557
SUb->addPred(Dep);
@@ -740,7 +740,8 @@ void ScheduleDAGInstrs::buildSchedGraph(AAResults *AA,
740740
const TargetSubtargetInfo &ST = MF.getSubtarget();
741741
bool UseAA = EnableAASchedMI.getNumOccurrences() > 0 ? EnableAASchedMI
742742
: ST.useAA();
743-
AAForDep = UseAA ? AA : nullptr;
743+
if (UseAA && AA)
744+
AAForDep.emplace(*AA);
744745

745746
BarrierChain = nullptr;
746747

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -191,8 +191,8 @@ namespace {
191191
/// candidate again.
192192
DenseMap<SDNode *, std::pair<SDNode *, unsigned>> StoreRootCountMap;
193193

194-
// AA - Used for DAG load/store alias analysis.
195-
AliasAnalysis *AA;
194+
// BatchAA - Used for DAG load/store alias analysis.
195+
BatchAAResults *BatchAA;
196196

197197
/// This caches all chains that have already been processed in
198198
/// DAGCombiner::getStoreMergeCandidates() and found to have no mergeable
@@ -247,9 +247,10 @@ namespace {
247247
SDValue visit(SDNode *N);
248248

249249
public:
250-
DAGCombiner(SelectionDAG &D, AliasAnalysis *AA, CodeGenOptLevel OL)
250+
DAGCombiner(SelectionDAG &D, BatchAAResults *BatchAA, CodeGenOptLevel OL)
251251
: DAG(D), TLI(D.getTargetLoweringInfo()),
252-
STI(D.getSubtarget().getSelectionDAGInfo()), OptLevel(OL), AA(AA) {
252+
STI(D.getSubtarget().getSelectionDAGInfo()), OptLevel(OL),
253+
BatchAA(BatchAA) {
253254
ForCodeSize = DAG.shouldOptForSize();
254255
DisableGenericCombines = STI && STI->disableGenericCombines(OptLevel);
255256

@@ -28918,7 +28919,7 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2891828919
UseAA = false;
2891928920
#endif
2892028921

28921-
if (UseAA && AA && MUC0.MMO->getValue() && MUC1.MMO->getValue() &&
28922+
if (UseAA && BatchAA && MUC0.MMO->getValue() && MUC1.MMO->getValue() &&
2892228923
Size0.hasValue() && Size1.hasValue() &&
2892328924
// Can't represent a scalable size + fixed offset in LocationSize
2892428925
(!Size0.isScalable() || SrcValOffset0 == 0) &&
@@ -28933,7 +28934,7 @@ bool DAGCombiner::mayAlias(SDNode *Op0, SDNode *Op1) const {
2893328934
Size0.isScalable() ? Size0 : LocationSize::precise(Overlap0);
2893428935
LocationSize Loc1 =
2893528936
Size1.isScalable() ? Size1 : LocationSize::precise(Overlap1);
28936-
if (AA->isNoAlias(
28937+
if (BatchAA->isNoAlias(
2893728938
MemoryLocation(MUC0.MMO->getValue(), Loc0,
2893828939
UseTBAA ? MUC0.MMO->getAAInfo() : AAMDNodes()),
2893928940
MemoryLocation(MUC1.MMO->getValue(), Loc1,
@@ -29239,8 +29240,8 @@ bool DAGCombiner::findBetterNeighborChains(StoreSDNode *St) {
2923929240
}
2924029241

2924129242
/// This is the entry point for the file.
29242-
void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis *AA,
29243+
void SelectionDAG::Combine(CombineLevel Level, BatchAAResults *BatchAA,
2924329244
CodeGenOptLevel OptLevel) {
2924429245
/// This is the main entry point to this class.
29245-
DAGCombiner(*this, AA, OptLevel).Run(Level);
29246+
DAGCombiner(*this, BatchAA, OptLevel).Run(Level);
2924629247
}

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -118,7 +118,7 @@ void ScheduleDAGFast::Schedule() {
118118
LiveRegCycles.resize(TRI->getNumRegs(), 0);
119119

120120
// Build the scheduling graph.
121-
BuildSchedGraph(nullptr);
121+
BuildSchedGraph();
122122

123123
LLVM_DEBUG(dump());
124124

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -370,7 +370,7 @@ void ScheduleDAGRRList::Schedule() {
370370
assert(Interferences.empty() && LRegsMap.empty() && "stale Interferences");
371371

372372
// Build the scheduling graph.
373-
BuildSchedGraph(nullptr);
373+
BuildSchedGraph();
374374

375375
LLVM_DEBUG(dump());
376376
Topo.MarkDirty();

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -536,7 +536,7 @@ void ScheduleDAGSDNodes::AddSchedEdges() {
536536
/// are input. This SUnit graph is similar to the SelectionDAG, but
537537
/// excludes nodes that aren't interesting to scheduling, and represents
538538
/// glued together nodes with a single SUnit.
539-
void ScheduleDAGSDNodes::BuildSchedGraph(AAResults *AA) {
539+
void ScheduleDAGSDNodes::BuildSchedGraph() {
540540
// Cluster certain nodes which should be scheduled together.
541541
ClusterNodes();
542542
// Populate the SUnits array.

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -94,7 +94,7 @@ class InstrItineraryData;
9494
/// are input. This SUnit graph is similar to the SelectionDAG, but
9595
/// excludes nodes that aren't interesting to scheduling, and represents
9696
/// flagged together nodes with a single SUnit.
97-
void BuildSchedGraph(AAResults *AA);
97+
void BuildSchedGraph();
9898

9999
/// InitNumRegDefsLeft - Determine the # of regs defined by this node.
100100
///

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGVLIW.cpp

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -59,14 +59,10 @@ class ScheduleDAGVLIW : public ScheduleDAGSDNodes {
5959
/// HazardRec - The hazard recognizer to use.
6060
ScheduleHazardRecognizer *HazardRec;
6161

62-
/// AA - AAResults for making memory reference queries.
63-
AAResults *AA;
64-
6562
public:
66-
ScheduleDAGVLIW(MachineFunction &mf, AAResults *aa,
67-
SchedulingPriorityQueue *availqueue)
68-
: ScheduleDAGSDNodes(mf), AvailableQueue(availqueue), AA(aa) {
69-
const TargetSubtargetInfo &STI = mf.getSubtarget();
63+
ScheduleDAGVLIW(MachineFunction &MF, SchedulingPriorityQueue *AvailableQueue)
64+
: ScheduleDAGSDNodes(MF), AvailableQueue(AvailableQueue) {
65+
const TargetSubtargetInfo &STI = MF.getSubtarget();
7066
HazardRec = STI.getInstrInfo()->CreateTargetHazardRecognizer(&STI, this);
7167
}
7268

@@ -91,7 +87,7 @@ void ScheduleDAGVLIW::Schedule() {
9187
<< " '" << BB->getName() << "' **********\n");
9288

9389
// Build the scheduling graph.
94-
BuildSchedGraph(AA);
90+
BuildSchedGraph();
9591

9692
AvailableQueue->initNodes(SUnits);
9793

@@ -267,5 +263,5 @@ void ScheduleDAGVLIW::listScheduleTopDown() {
267263
/// createVLIWDAGScheduler - This creates a top-down list scheduler.
268264
ScheduleDAGSDNodes *llvm::createVLIWDAGScheduler(SelectionDAGISel *IS,
269265
CodeGenOptLevel) {
270-
return new ScheduleDAGVLIW(*IS->MF, IS->AA, new ResourcePriorityQueue(IS));
266+
return new ScheduleDAGVLIW(*IS->MF, new ResourcePriorityQueue(IS));
271267
}

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -8126,13 +8126,11 @@ static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl,
81268126
}
81278127
}
81288128

8129-
static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
8130-
SDValue Chain, SDValue Dst, SDValue Src,
8131-
uint64_t Size, Align Alignment,
8132-
bool isVol, bool AlwaysInline,
8133-
MachinePointerInfo DstPtrInfo,
8134-
MachinePointerInfo SrcPtrInfo,
8135-
const AAMDNodes &AAInfo, AAResults *AA) {
8129+
static SDValue getMemcpyLoadsAndStores(
8130+
SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
8131+
uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline,
8132+
MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo,
8133+
const AAMDNodes &AAInfo, BatchAAResults *BatchAA) {
81368134
// Turn a memcpy of undef to nop.
81378135
// FIXME: We need to honor volatile even is Src is undef.
81388136
if (Src.isUndef())
@@ -8198,8 +8196,8 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl,
81988196

81998197
const Value *SrcVal = dyn_cast_if_present<const Value *>(SrcPtrInfo.V);
82008198
bool isConstant =
8201-
AA && SrcVal &&
8202-
AA->pointsToConstantMemory(MemoryLocation(SrcVal, Size, AAInfo));
8199+
BatchAA && SrcVal &&
8200+
BatchAA->pointsToConstantMemory(MemoryLocation(SrcVal, Size, AAInfo));
82038201

82048202
MachineMemOperand::Flags MMOFlags =
82058203
isVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
@@ -8584,7 +8582,8 @@ SDValue SelectionDAG::getMemcpy(
85848582
SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size,
85858583
Align Alignment, bool isVol, bool AlwaysInline, const CallInst *CI,
85868584
std::optional<bool> OverrideTailCall, MachinePointerInfo DstPtrInfo,
8587-
MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo, AAResults *AA) {
8585+
MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo,
8586+
BatchAAResults *BatchAA) {
85888587
// Check to see if we should lower the memcpy to loads and stores first.
85898588
// For cases within the target-specified limits, this is the best choice.
85908589
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
@@ -8595,7 +8594,7 @@ SDValue SelectionDAG::getMemcpy(
85958594

85968595
SDValue Result = getMemcpyLoadsAndStores(
85978596
*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment,
8598-
isVol, false, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8597+
isVol, false, DstPtrInfo, SrcPtrInfo, AAInfo, BatchAA);
85998598
if (Result.getNode())
86008599
return Result;
86018600
}
@@ -8616,7 +8615,7 @@ SDValue SelectionDAG::getMemcpy(
86168615
assert(ConstantSize && "AlwaysInline requires a constant size!");
86178616
return getMemcpyLoadsAndStores(
86188617
*this, dl, Chain, Dst, Src, ConstantSize->getZExtValue(), Alignment,
8619-
isVol, true, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8618+
isVol, true, DstPtrInfo, SrcPtrInfo, AAInfo, BatchAA);
86208619
}
86218620

86228621
checkAddrSpaceIsValidForLibcall(TLI, DstPtrInfo.getAddrSpace());
@@ -8711,7 +8710,8 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
87118710
std::optional<bool> OverrideTailCall,
87128711
MachinePointerInfo DstPtrInfo,
87138712
MachinePointerInfo SrcPtrInfo,
8714-
const AAMDNodes &AAInfo, AAResults *AA) {
8713+
const AAMDNodes &AAInfo,
8714+
BatchAAResults *BatchAA) {
87158715
// Check to see if we should lower the memmove to loads and stores first.
87168716
// For cases within the target-specified limits, this is the best choice.
87178717
ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);

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