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michaelmaitlandmichaelmaitland
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[RISCV] Add sifive-p670 processor (#79015)
This is an OOO core that has a vector unit. For more information see https://www.sifive.com/cores/performance-p650-670. Scheduler model and other tuning will come in separate patches.
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‎clang/test/Driver/riscv-cpus.c

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@@ -247,7 +247,54 @@
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbb"
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// MCPU-SIFIVE-P450-SAME: "-target-feature" "+zbs"
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// MCPU-SIFIVE-P450-SAME: "-target-abi" "lp64d"
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//
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// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p670 | FileCheck -check-prefix=MCPU-SIFIVE-P670 %s
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// MCPU-SIFIVE-P670: "-target-cpu" "sifive-p670"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+m"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+a"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+f"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+d"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+c"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+v"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zic64b"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicbom"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicbop"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicboz"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccamoa"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccif"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicclsm"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+ziccrse"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zicsr"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zifencei"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintntl"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihintpause"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zihpm"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+za64rs"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zfhmin"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zba"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zbb"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zbs"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbb"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvbc"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32f"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve32x"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64d"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64f"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zve64x"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkg"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkn"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvknc"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkned"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkng"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvknhb"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvks"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksc"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksed"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksg"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvksh"
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// MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt"
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// MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d"
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// Check failed cases
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// RUN: not %clang --target=riscv32 -### -c %s 2>&1 -mcpu=generic-rv321 | FileCheck -check-prefix=FAIL-MCPU-NAME %s

‎clang/test/Misc/target-invalid-cpu-note.c

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@@ -85,12 +85,12 @@
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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
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// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
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// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}

‎llvm/docs/ReleaseNotes.rst

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@@ -180,6 +180,7 @@ Changes to the RISC-V Backend
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and Zic64b extensions which were introduced as a part of the RISC-V Profiles
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specification.
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* The Smepmp 1.0 extension is now supported.
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* ``-mcpu=sifive-p670`` was added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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@@ -245,6 +245,43 @@ def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", SiFiveP400Model,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion]>;
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def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", NoSchedModel,
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[Feature64Bit,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtZa64rs,
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FeatureStdExtZic64b,
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FeatureStdExtZicbop,
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FeatureStdExtZicbom,
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FeatureStdExtZicboz,
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FeatureStdExtZiccamoa,
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FeatureStdExtZiccif,
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FeatureStdExtZicclsm,
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FeatureStdExtZiccrse,
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FeatureStdExtZihintntl,
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FeatureStdExtZihintpause,
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FeatureStdExtZihpm,
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FeatureStdExtZba,
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FeatureStdExtZbb,
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FeatureStdExtZbs,
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FeatureStdExtZfhmin,
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FeatureStdExtV,
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FeatureStdExtZvl128b,
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FeatureStdExtZvbb,
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FeatureStdExtZvknc,
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FeatureStdExtZvkng,
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FeatureStdExtZvksc,
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FeatureStdExtZvksg,
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FeatureFastUnalignedAccess],
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[TuneNoDefaultUnroll,
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TuneConditionalCompressedMoveFusion,
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TuneLUIADDIFusion,
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TuneAUIPCADDIFusion]>;
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def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base",
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SyntacoreSCR1Model,
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[Feature32Bit,

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