Skip to content

Commit 5883f6f

Browse files
RKSimonRKSimon
committed
[X86] Add AVX tests buildvec-insertvec.ll
1 parent b392fb3 commit 5883f6f

File tree

1 file changed

+211
-42
lines changed

1 file changed

+211
-42
lines changed

‎llvm/test/CodeGen/X86/buildvec-insertvec.ll

Lines changed: 211 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE2
3-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=CHECK --check-prefix=SSE41
2+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE,SSE2
3+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=CHECK,SSE,SSE41
4+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX,AVX1
5+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
46

57
define void @foo(<3 x float> %in, <4 x i8>* nocapture %out) nounwind {
68
; SSE2-LABEL: foo:
@@ -26,6 +28,15 @@ define void @foo(<3 x float> %in, <4 x i8>* nocapture %out) nounwind {
2628
; SSE41-NEXT: pinsrb $3, %eax, %xmm0
2729
; SSE41-NEXT: movd %xmm0, (%rdi)
2830
; SSE41-NEXT: retq
31+
;
32+
; AVX-LABEL: foo:
33+
; AVX: # %bb.0:
34+
; AVX-NEXT: vcvttps2dq %xmm0, %xmm0
35+
; AVX-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4,8],zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u]
36+
; AVX-NEXT: movl $255, %eax
37+
; AVX-NEXT: vpinsrb $3, %eax, %xmm0, %xmm0
38+
; AVX-NEXT: vmovd %xmm0, (%rdi)
39+
; AVX-NEXT: retq
2940
%t0 = fptoui <3 x float> %in to <3 x i8>
3041
%t1 = shufflevector <3 x i8> %t0, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
3142
%t2 = insertelement <4 x i8> %t1, i8 -1, i32 3
@@ -52,6 +63,11 @@ define <4 x float> @test_negative_zero_1(<4 x float> %A) {
5263
; SSE41: # %bb.0: # %entry
5364
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero
5465
; SSE41-NEXT: retq
66+
;
67+
; AVX-LABEL: test_negative_zero_1:
68+
; AVX: # %bb.0: # %entry
69+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2],zero
70+
; AVX-NEXT: retq
5571
entry:
5672
%0 = extractelement <4 x float> %A, i32 0
5773
%1 = insertelement <4 x float> undef, float %0, i32 0
@@ -74,6 +90,11 @@ define <2 x double> @test_negative_zero_2(<2 x double> %A) {
7490
; SSE41: # %bb.0: # %entry
7591
; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]
7692
; SSE41-NEXT: retq
93+
;
94+
; AVX-LABEL: test_negative_zero_2:
95+
; AVX: # %bb.0: # %entry
96+
; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]
97+
; AVX-NEXT: retq
7798
entry:
7899
%0 = extractelement <2 x double> %A, i32 0
79100
%1 = insertelement <2 x double> undef, double %0, i32 0
@@ -95,6 +116,13 @@ define <4 x float> @test_buildvector_v4f32_register(float %f0, float %f1, float
95116
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
96117
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
97118
; SSE41-NEXT: retq
119+
;
120+
; AVX-LABEL: test_buildvector_v4f32_register:
121+
; AVX: # %bb.0:
122+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
123+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
124+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[0]
125+
; AVX-NEXT: retq
98126
%ins0 = insertelement <4 x float> undef, float %f0, i32 0
99127
%ins1 = insertelement <4 x float> %ins0, float %f1, i32 1
100128
%ins2 = insertelement <4 x float> %ins1, float %f2, i32 2
@@ -121,6 +149,14 @@ define <4 x float> @test_buildvector_v4f32_load(float* %p0, float* %p1, float* %
121149
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
122150
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
123151
; SSE41-NEXT: retq
152+
;
153+
; AVX-LABEL: test_buildvector_v4f32_load:
154+
; AVX: # %bb.0:
155+
; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero
156+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3]
157+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3]
158+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
159+
; AVX-NEXT: retq
124160
%f0 = load float, float* %p0, align 4
125161
%f1 = load float, float* %p1, align 4
126162
%f2 = load float, float* %p2, align 4
@@ -147,6 +183,13 @@ define <4 x float> @test_buildvector_v4f32_partial_load(float %f0, float %f1, fl
147183
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
148184
; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
149185
; SSE41-NEXT: retq
186+
;
187+
; AVX-LABEL: test_buildvector_v4f32_partial_load:
188+
; AVX: # %bb.0:
189+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
190+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],xmm2[0],xmm0[3]
191+
; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0]
192+
; AVX-NEXT: retq
150193
%f3 = load float, float* %p3, align 4
151194
%ins0 = insertelement <4 x float> undef, float %f0, i32 0
152195
%ins1 = insertelement <4 x float> %ins0, float %f1, i32 1
@@ -174,6 +217,14 @@ define <4 x i32> @test_buildvector_v4i32_register(i32 %a0, i32 %a1, i32 %a2, i32
174217
; SSE41-NEXT: pinsrd $2, %edx, %xmm0
175218
; SSE41-NEXT: pinsrd $3, %ecx, %xmm0
176219
; SSE41-NEXT: retq
220+
;
221+
; AVX-LABEL: test_buildvector_v4i32_register:
222+
; AVX: # %bb.0:
223+
; AVX-NEXT: vmovd %edi, %xmm0
224+
; AVX-NEXT: vpinsrd $1, %esi, %xmm0, %xmm0
225+
; AVX-NEXT: vpinsrd $2, %edx, %xmm0, %xmm0
226+
; AVX-NEXT: vpinsrd $3, %ecx, %xmm0, %xmm0
227+
; AVX-NEXT: retq
177228
%ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0
178229
%ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1
179230
%ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2
@@ -195,6 +246,12 @@ define <4 x i32> @test_buildvector_v4i32_partial(i32 %a0, i32 %a3) {
195246
; SSE41-NEXT: movd %edi, %xmm0
196247
; SSE41-NEXT: pinsrd $3, %esi, %xmm0
197248
; SSE41-NEXT: retq
249+
;
250+
; AVX-LABEL: test_buildvector_v4i32_partial:
251+
; AVX: # %bb.0:
252+
; AVX-NEXT: vmovd %edi, %xmm0
253+
; AVX-NEXT: vpinsrd $3, %esi, %xmm0, %xmm0
254+
; AVX-NEXT: retq
198255
%ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0
199256
%ins1 = insertelement <4 x i32> %ins0, i32 undef, i32 1
200257
%ins2 = insertelement <4 x i32> %ins1, i32 undef, i32 2
@@ -203,14 +260,23 @@ define <4 x i32> @test_buildvector_v4i32_partial(i32 %a0, i32 %a3) {
203260
}
204261

205262
define <4 x i32> @test_buildvector_v4i32_register_zero(i32 %a0, i32 %a2, i32 %a3) {
206-
; CHECK-LABEL: test_buildvector_v4i32_register_zero:
207-
; CHECK: # %bb.0:
208-
; CHECK-NEXT: movd %edx, %xmm0
209-
; CHECK-NEXT: movd %esi, %xmm1
210-
; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
211-
; CHECK-NEXT: movd %edi, %xmm0
212-
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
213-
; CHECK-NEXT: retq
263+
; SSE-LABEL: test_buildvector_v4i32_register_zero:
264+
; SSE: # %bb.0:
265+
; SSE-NEXT: movd %edx, %xmm0
266+
; SSE-NEXT: movd %esi, %xmm1
267+
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
268+
; SSE-NEXT: movd %edi, %xmm0
269+
; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
270+
; SSE-NEXT: retq
271+
;
272+
; AVX-LABEL: test_buildvector_v4i32_register_zero:
273+
; AVX: # %bb.0:
274+
; AVX-NEXT: vmovd %edx, %xmm0
275+
; AVX-NEXT: vmovd %esi, %xmm1
276+
; AVX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
277+
; AVX-NEXT: vmovd %edi, %xmm1
278+
; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
279+
; AVX-NEXT: retq
214280
%ins0 = insertelement <4 x i32> undef, i32 %a0, i32 0
215281
%ins1 = insertelement <4 x i32> %ins0, i32 0, i32 1
216282
%ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2
@@ -219,14 +285,23 @@ define <4 x i32> @test_buildvector_v4i32_register_zero(i32 %a0, i32 %a2, i32 %a3
219285
}
220286

221287
define <4 x i32> @test_buildvector_v4i32_register_zero_2(i32 %a1, i32 %a2, i32 %a3) {
222-
; CHECK-LABEL: test_buildvector_v4i32_register_zero_2:
223-
; CHECK: # %bb.0:
224-
; CHECK-NEXT: movd %edx, %xmm0
225-
; CHECK-NEXT: movd %esi, %xmm1
226-
; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
227-
; CHECK-NEXT: movd %edi, %xmm0
228-
; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,1]
229-
; CHECK-NEXT: retq
288+
; SSE-LABEL: test_buildvector_v4i32_register_zero_2:
289+
; SSE: # %bb.0:
290+
; SSE-NEXT: movd %edx, %xmm0
291+
; SSE-NEXT: movd %esi, %xmm1
292+
; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
293+
; SSE-NEXT: movd %edi, %xmm0
294+
; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm1[0,1]
295+
; SSE-NEXT: retq
296+
;
297+
; AVX-LABEL: test_buildvector_v4i32_register_zero_2:
298+
; AVX: # %bb.0:
299+
; AVX-NEXT: vmovd %edx, %xmm0
300+
; AVX-NEXT: vmovd %esi, %xmm1
301+
; AVX-NEXT: vpunpckldq {{.*#+}} xmm0 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
302+
; AVX-NEXT: vmovd %edi, %xmm1
303+
; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[1,0],xmm0[0,1]
304+
; AVX-NEXT: retq
230305
%ins0 = insertelement <4 x i32> undef, i32 0, i32 0
231306
%ins1 = insertelement <4 x i32> %ins0, i32 %a1, i32 1
232307
%ins2 = insertelement <4 x i32> %ins1, i32 %a2, i32 2
@@ -265,6 +340,18 @@ define <8 x i16> @test_buildvector_v8i16_register(i16 %a0, i16 %a1, i16 %a2, i16
265340
; SSE41-NEXT: pinsrw $6, {{[0-9]+}}(%rsp), %xmm0
266341
; SSE41-NEXT: pinsrw $7, {{[0-9]+}}(%rsp), %xmm0
267342
; SSE41-NEXT: retq
343+
;
344+
; AVX-LABEL: test_buildvector_v8i16_register:
345+
; AVX: # %bb.0:
346+
; AVX-NEXT: vmovd %edi, %xmm0
347+
; AVX-NEXT: vpinsrw $1, %esi, %xmm0, %xmm0
348+
; AVX-NEXT: vpinsrw $2, %edx, %xmm0, %xmm0
349+
; AVX-NEXT: vpinsrw $3, %ecx, %xmm0, %xmm0
350+
; AVX-NEXT: vpinsrw $4, %r8d, %xmm0, %xmm0
351+
; AVX-NEXT: vpinsrw $5, %r9d, %xmm0, %xmm0
352+
; AVX-NEXT: vpinsrw $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0
353+
; AVX-NEXT: vpinsrw $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0
354+
; AVX-NEXT: retq
268355
%ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0
269356
%ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1
270357
%ins2 = insertelement <8 x i16> %ins1, i16 %a2, i32 2
@@ -277,14 +364,23 @@ define <8 x i16> @test_buildvector_v8i16_register(i16 %a0, i16 %a1, i16 %a2, i16
277364
}
278365

279366
define <8 x i16> @test_buildvector_v8i16_partial(i16 %a1, i16 %a3, i16 %a4, i16 %a5) {
280-
; CHECK-LABEL: test_buildvector_v8i16_partial:
281-
; CHECK: # %bb.0:
282-
; CHECK-NEXT: pxor %xmm0, %xmm0
283-
; CHECK-NEXT: pinsrw $1, %edi, %xmm0
284-
; CHECK-NEXT: pinsrw $3, %esi, %xmm0
285-
; CHECK-NEXT: pinsrw $4, %edx, %xmm0
286-
; CHECK-NEXT: pinsrw $5, %ecx, %xmm0
287-
; CHECK-NEXT: retq
367+
; SSE-LABEL: test_buildvector_v8i16_partial:
368+
; SSE: # %bb.0:
369+
; SSE-NEXT: pxor %xmm0, %xmm0
370+
; SSE-NEXT: pinsrw $1, %edi, %xmm0
371+
; SSE-NEXT: pinsrw $3, %esi, %xmm0
372+
; SSE-NEXT: pinsrw $4, %edx, %xmm0
373+
; SSE-NEXT: pinsrw $5, %ecx, %xmm0
374+
; SSE-NEXT: retq
375+
;
376+
; AVX-LABEL: test_buildvector_v8i16_partial:
377+
; AVX: # %bb.0:
378+
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
379+
; AVX-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0
380+
; AVX-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0
381+
; AVX-NEXT: vpinsrw $4, %edx, %xmm0, %xmm0
382+
; AVX-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0
383+
; AVX-NEXT: retq
288384
%ins0 = insertelement <8 x i16> undef, i16 undef, i32 0
289385
%ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1
290386
%ins2 = insertelement <8 x i16> %ins1, i16 undef, i32 2
@@ -297,14 +393,23 @@ define <8 x i16> @test_buildvector_v8i16_partial(i16 %a1, i16 %a3, i16 %a4, i16
297393
}
298394

299395
define <8 x i16> @test_buildvector_v8i16_register_zero(i16 %a0, i16 %a3, i16 %a4, i16 %a5) {
300-
; CHECK-LABEL: test_buildvector_v8i16_register_zero:
301-
; CHECK: # %bb.0:
302-
; CHECK-NEXT: movzwl %di, %eax
303-
; CHECK-NEXT: movd %eax, %xmm0
304-
; CHECK-NEXT: pinsrw $3, %esi, %xmm0
305-
; CHECK-NEXT: pinsrw $4, %edx, %xmm0
306-
; CHECK-NEXT: pinsrw $5, %ecx, %xmm0
307-
; CHECK-NEXT: retq
396+
; SSE-LABEL: test_buildvector_v8i16_register_zero:
397+
; SSE: # %bb.0:
398+
; SSE-NEXT: movzwl %di, %eax
399+
; SSE-NEXT: movd %eax, %xmm0
400+
; SSE-NEXT: pinsrw $3, %esi, %xmm0
401+
; SSE-NEXT: pinsrw $4, %edx, %xmm0
402+
; SSE-NEXT: pinsrw $5, %ecx, %xmm0
403+
; SSE-NEXT: retq
404+
;
405+
; AVX-LABEL: test_buildvector_v8i16_register_zero:
406+
; AVX: # %bb.0:
407+
; AVX-NEXT: movzwl %di, %eax
408+
; AVX-NEXT: vmovd %eax, %xmm0
409+
; AVX-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0
410+
; AVX-NEXT: vpinsrw $4, %edx, %xmm0, %xmm0
411+
; AVX-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0
412+
; AVX-NEXT: retq
308413
%ins0 = insertelement <8 x i16> undef, i16 %a0, i32 0
309414
%ins1 = insertelement <8 x i16> %ins0, i16 0, i32 1
310415
%ins2 = insertelement <8 x i16> %ins1, i16 0, i32 2
@@ -317,14 +422,23 @@ define <8 x i16> @test_buildvector_v8i16_register_zero(i16 %a0, i16 %a3, i16 %a4
317422
}
318423

319424
define <8 x i16> @test_buildvector_v8i16_register_zero_2(i16 %a1, i16 %a3, i16 %a4, i16 %a5) {
320-
; CHECK-LABEL: test_buildvector_v8i16_register_zero_2:
321-
; CHECK: # %bb.0:
322-
; CHECK-NEXT: pxor %xmm0, %xmm0
323-
; CHECK-NEXT: pinsrw $1, %edi, %xmm0
324-
; CHECK-NEXT: pinsrw $3, %esi, %xmm0
325-
; CHECK-NEXT: pinsrw $4, %edx, %xmm0
326-
; CHECK-NEXT: pinsrw $5, %ecx, %xmm0
327-
; CHECK-NEXT: retq
425+
; SSE-LABEL: test_buildvector_v8i16_register_zero_2:
426+
; SSE: # %bb.0:
427+
; SSE-NEXT: pxor %xmm0, %xmm0
428+
; SSE-NEXT: pinsrw $1, %edi, %xmm0
429+
; SSE-NEXT: pinsrw $3, %esi, %xmm0
430+
; SSE-NEXT: pinsrw $4, %edx, %xmm0
431+
; SSE-NEXT: pinsrw $5, %ecx, %xmm0
432+
; SSE-NEXT: retq
433+
;
434+
; AVX-LABEL: test_buildvector_v8i16_register_zero_2:
435+
; AVX: # %bb.0:
436+
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
437+
; AVX-NEXT: vpinsrw $1, %edi, %xmm0, %xmm0
438+
; AVX-NEXT: vpinsrw $3, %esi, %xmm0, %xmm0
439+
; AVX-NEXT: vpinsrw $4, %edx, %xmm0, %xmm0
440+
; AVX-NEXT: vpinsrw $5, %ecx, %xmm0, %xmm0
441+
; AVX-NEXT: retq
328442
%ins0 = insertelement <8 x i16> undef, i16 0, i32 0
329443
%ins1 = insertelement <8 x i16> %ins0, i16 %a1, i32 1
330444
%ins2 = insertelement <8 x i16> %ins1, i16 0, i32 2
@@ -391,6 +505,26 @@ define <16 x i8> @test_buildvector_v16i8_register(i8 %a0, i8 %a1, i8 %a2, i8 %a3
391505
; SSE41-NEXT: pinsrb $14, {{[0-9]+}}(%rsp), %xmm0
392506
; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0
393507
; SSE41-NEXT: retq
508+
;
509+
; AVX-LABEL: test_buildvector_v16i8_register:
510+
; AVX: # %bb.0:
511+
; AVX-NEXT: vmovd %edi, %xmm0
512+
; AVX-NEXT: vpinsrb $1, %esi, %xmm0, %xmm0
513+
; AVX-NEXT: vpinsrb $2, %edx, %xmm0, %xmm0
514+
; AVX-NEXT: vpinsrb $3, %ecx, %xmm0, %xmm0
515+
; AVX-NEXT: vpinsrb $4, %r8d, %xmm0, %xmm0
516+
; AVX-NEXT: vpinsrb $5, %r9d, %xmm0, %xmm0
517+
; AVX-NEXT: vpinsrb $6, {{[0-9]+}}(%rsp), %xmm0, %xmm0
518+
; AVX-NEXT: vpinsrb $7, {{[0-9]+}}(%rsp), %xmm0, %xmm0
519+
; AVX-NEXT: vpinsrb $8, {{[0-9]+}}(%rsp), %xmm0, %xmm0
520+
; AVX-NEXT: vpinsrb $9, {{[0-9]+}}(%rsp), %xmm0, %xmm0
521+
; AVX-NEXT: vpinsrb $10, {{[0-9]+}}(%rsp), %xmm0, %xmm0
522+
; AVX-NEXT: vpinsrb $11, {{[0-9]+}}(%rsp), %xmm0, %xmm0
523+
; AVX-NEXT: vpinsrb $12, {{[0-9]+}}(%rsp), %xmm0, %xmm0
524+
; AVX-NEXT: vpinsrb $13, {{[0-9]+}}(%rsp), %xmm0, %xmm0
525+
; AVX-NEXT: vpinsrb $14, {{[0-9]+}}(%rsp), %xmm0, %xmm0
526+
; AVX-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0
527+
; AVX-NEXT: retq
394528
%ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0
395529
%ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1
396530
%ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2
@@ -434,6 +568,17 @@ define <16 x i8> @test_buildvector_v16i8_partial(i8 %a2, i8 %a6, i8 %a8, i8 %a11
434568
; SSE41-NEXT: pinsrb $12, %r8d, %xmm0
435569
; SSE41-NEXT: pinsrb $15, %r9d, %xmm0
436570
; SSE41-NEXT: retq
571+
;
572+
; AVX-LABEL: test_buildvector_v16i8_partial:
573+
; AVX: # %bb.0:
574+
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
575+
; AVX-NEXT: vpinsrb $2, %edi, %xmm0, %xmm0
576+
; AVX-NEXT: vpinsrb $6, %esi, %xmm0, %xmm0
577+
; AVX-NEXT: vpinsrb $8, %edx, %xmm0, %xmm0
578+
; AVX-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0
579+
; AVX-NEXT: vpinsrb $12, %r8d, %xmm0, %xmm0
580+
; AVX-NEXT: vpinsrb $15, %r9d, %xmm0, %xmm0
581+
; AVX-NEXT: retq
437582
%ins0 = insertelement <16 x i8> undef, i8 undef, i32 0
438583
%ins1 = insertelement <16 x i8> %ins0, i8 undef, i32 1
439584
%ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2
@@ -484,6 +629,18 @@ define <16 x i8> @test_buildvector_v16i8_register_zero(i8 %a0, i8 %a4, i8 %a6, i
484629
; SSE41-NEXT: pinsrb $12, %r9d, %xmm0
485630
; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0
486631
; SSE41-NEXT: retq
632+
;
633+
; AVX-LABEL: test_buildvector_v16i8_register_zero:
634+
; AVX: # %bb.0:
635+
; AVX-NEXT: movzbl %dil, %eax
636+
; AVX-NEXT: vmovd %eax, %xmm0
637+
; AVX-NEXT: vpinsrb $4, %esi, %xmm0, %xmm0
638+
; AVX-NEXT: vpinsrb $6, %edx, %xmm0, %xmm0
639+
; AVX-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0
640+
; AVX-NEXT: vpinsrb $11, %r8d, %xmm0, %xmm0
641+
; AVX-NEXT: vpinsrb $12, %r9d, %xmm0, %xmm0
642+
; AVX-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0
643+
; AVX-NEXT: retq
487644
%ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0
488645
%ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1
489646
%ins2 = insertelement <16 x i8> %ins1, i8 0, i32 2
@@ -535,6 +692,18 @@ define <16 x i8> @test_buildvector_v16i8_register_zero_2(i8 %a2, i8 %a3, i8 %a6,
535692
; SSE41-NEXT: pinsrb $12, %r9d, %xmm0
536693
; SSE41-NEXT: pinsrb $15, {{[0-9]+}}(%rsp), %xmm0
537694
; SSE41-NEXT: retq
695+
;
696+
; AVX-LABEL: test_buildvector_v16i8_register_zero_2:
697+
; AVX: # %bb.0:
698+
; AVX-NEXT: vpxor %xmm0, %xmm0, %xmm0
699+
; AVX-NEXT: vpinsrb $2, %edi, %xmm0, %xmm0
700+
; AVX-NEXT: vpinsrb $3, %esi, %xmm0, %xmm0
701+
; AVX-NEXT: vpinsrb $6, %edx, %xmm0, %xmm0
702+
; AVX-NEXT: vpinsrb $8, %ecx, %xmm0, %xmm0
703+
; AVX-NEXT: vpinsrb $11, %r8d, %xmm0, %xmm0
704+
; AVX-NEXT: vpinsrb $12, %r9d, %xmm0, %xmm0
705+
; AVX-NEXT: vpinsrb $15, {{[0-9]+}}(%rsp), %xmm0, %xmm0
706+
; AVX-NEXT: retq
538707
%ins0 = insertelement <16 x i8> undef, i8 0, i32 0
539708
%ins1 = insertelement <16 x i8> %ins0, i8 0, i32 1
540709
%ins2 = insertelement <16 x i8> %ins1, i8 %a2, i32 2

0 commit comments

Comments
 (0)