Skip to content

Commit 52ed8e0

Browse files
committed
[RISCV] Add B extension
It seems that we have `B` extension again: https://github.com/riscv/riscv-b According to the spec, `B` extension represents the collection of the `Zba`, `Zbb`, `Zbs` extensions. Though it hasn't been ratified, I set its version to `1.0`.
1 parent 6ae7f66 commit 52ed8e0

File tree

5 files changed

+28
-0
lines changed

5 files changed

+28
-0
lines changed

clang/test/Preprocessor/riscv-target-features.c

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55

66
// CHECK-NOT: __riscv_a {{.*$}}
77
// CHECK-NOT: __riscv_atomic
8+
// CHECK-NOT: __riscv_b {{.*$}}
89
// CHECK-NOT: __riscv_c {{.*$}}
910
// CHECK-NOT: __riscv_compressed {{.*$}}
1011
// CHECK-NOT: __riscv_d {{.*$}}
@@ -150,6 +151,17 @@
150151
// CHECK-A-EXT: __riscv_a 2001000{{$}}
151152
// CHECK-A-EXT: __riscv_atomic 1
152153

154+
// RUN: %clang --target=riscv32-unknown-linux-gnu \
155+
// RUN: -march=rv32ib -x c -E -dM %s \
156+
// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
157+
// RUN: %clang --target=riscv64-unknown-linux-gnu \
158+
// RUN: -march=rv64ib -x c -E -dM %s \
159+
// RUN: -o - | FileCheck --check-prefix=CHECK-B-EXT %s
160+
// CHECK-B-EXT: __riscv_b 1000000{{$}}
161+
// CHECK-B-EXT: __riscv_zba 1000000{{$}}
162+
// CHECK-B-EXT: __riscv_zbb 1000000{{$}}
163+
// CHECK-B-EXT: __riscv_zbs 1000000{{$}}
164+
153165
// RUN: %clang --target=riscv32-unknown-linux-gnu \
154166
// RUN: -march=rv32ic -x c -E -dM %s \
155167
// RUN: -o - | FileCheck --check-prefix=CHECK-C-EXT %s

llvm/docs/RISCVUsage.rst

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -85,6 +85,7 @@ on support follow.
8585
Extension Status
8686
=============== =========================================================
8787
``A`` Supported
88+
``B`` Supported
8889
``C`` Supported
8990
``D`` Supported
9091
``F`` Supported

llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ static const char *RISCVGImplications[] = {
5151
// NOTE: This table should be sorted alphabetically by extension name.
5252
static const RISCVSupportedExtension SupportedExtensions[] = {
5353
{"a", RISCVExtensionVersion{2, 1}},
54+
{"b", RISCVExtensionVersion{1, 0}},
5455
{"c", RISCVExtensionVersion{2, 0}},
5556
{"d", RISCVExtensionVersion{2, 2}},
5657
{"e", RISCVExtensionVersion{2, 0}},
@@ -997,6 +998,7 @@ Error RISCVISAInfo::checkDependency() {
997998
return Error::success();
998999
}
9991000

1001+
static const char *ImpliedExtsB[] = {"zba", "zbb", "zbs"};
10001002
static const char *ImpliedExtsD[] = {"f"};
10011003
static const char *ImpliedExtsF[] = {"zicsr"};
10021004
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
@@ -1071,6 +1073,7 @@ struct ImpliedExtsEntry {
10711073

10721074
// Note: The table needs to be sorted by name.
10731075
static constexpr ImpliedExtsEntry ImpliedExts[] = {
1076+
{{"b"}, {ImpliedExtsB}},
10741077
{{"d"}, {ImpliedExtsD}},
10751078
{{"f"}, {ImpliedExtsF}},
10761079
{{"v"}, {ImpliedExtsV}},

llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -202,6 +202,14 @@ def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">,
202202
AssemblerPredicate<(all_of FeatureStdExtZbs),
203203
"'Zbs' (Single-Bit Instructions)">;
204204

205+
def FeatureStdExtB
206+
: SubtargetFeature<"b", "HasStdExtB", "true",
207+
"'B' (the collection of the Zba, Zbb, Zbs extensions)",
208+
[FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZbs]>;
209+
def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
210+
AssemblerPredicate<(all_of FeatureStdExtB),
211+
"'B' (the collection of the Zba, Zbb, Zbs extensions)">;
212+
205213
def FeatureStdExtZbkb
206214
: SubtargetFeature<"zbkb", "HasStdExtZbkb", "true",
207215
"'Zbkb' (Bitmanip instructions for Cryptography)">;

llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@
55
; RUN: llc -mtriple=riscv32 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32ZMMUL %s
66
; RUN: llc -mtriple=riscv32 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV32MZMMUL %s
77
; RUN: llc -mtriple=riscv32 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV32A %s
8+
; RUN: llc -mtriple=riscv32 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV32B %s
89
; RUN: llc -mtriple=riscv32 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV32F %s
910
; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV32D %s
1011
; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV32C %s
@@ -100,6 +101,7 @@
100101
; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s
101102
; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s
102103
; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s
104+
; RUN: llc -mtriple=riscv64 -mattr=+b %s -o - | FileCheck --check-prefixes=CHECK,RV64B %s
103105
; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s
104106
; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s
105107
; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s
@@ -195,6 +197,7 @@
195197
; RV32ZMMUL: .attribute 5, "rv32i2p1_zmmul1p0"
196198
; RV32MZMMUL: .attribute 5, "rv32i2p1_m2p0_zmmul1p0"
197199
; RV32A: .attribute 5, "rv32i2p1_a2p1"
200+
; RV32B: .attribute 5, "rv32i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
198201
; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
199202
; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
200203
; RV32C: .attribute 5, "rv32i2p1_c2p0"
@@ -289,6 +292,7 @@
289292
; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0"
290293
; RV64MZMMUL: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
291294
; RV64A: .attribute 5, "rv64i2p1_a2p1"
295+
; RV64B: .attribute 5, "rv64i2p1_b1p0_zba1p0_zbb1p0_zbs1p0"
292296
; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
293297
; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
294298
; RV64C: .attribute 5, "rv64i2p1_c2p0"

0 commit comments

Comments
 (0)