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[RISCV] Add isel support for scalar STRICT_FADD/FSUB/FMUL/FDIV/FSQRT.
Test that STRICT_FMINNUM/FMAXNUM are lowered to libcalls for f32/f64. The RISC-V instructions don't match the behavior of fmin/fmax libcalls with respect to SNaN. Promoting FMINNUM/FMAXNUM for f16 needs more work outside of the RISC-V backend. Reviewed By: asb, arcbbb Differential Revision: https://reviews.llvm.org/D115680
1 parent 0319d4a commit 3926893

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7 files changed

+1862
-27
lines changed

7 files changed

+1862
-27
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -330,6 +330,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
330330
setOperationAction(ISD::LLRINT, MVT::f16, Legal);
331331
setOperationAction(ISD::LROUND, MVT::f16, Legal);
332332
setOperationAction(ISD::LLROUND, MVT::f16, Legal);
333+
setOperationAction(ISD::STRICT_FADD, MVT::f16, Legal);
334+
setOperationAction(ISD::STRICT_FMA, MVT::f16, Legal);
335+
setOperationAction(ISD::STRICT_FSUB, MVT::f16, Legal);
336+
setOperationAction(ISD::STRICT_FMUL, MVT::f16, Legal);
337+
setOperationAction(ISD::STRICT_FDIV, MVT::f16, Legal);
338+
setOperationAction(ISD::STRICT_FSQRT, MVT::f16, Legal);
333339
for (auto CC : FPCCToExpand)
334340
setCondCodeAction(CC, MVT::f16, Expand);
335341
setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
@@ -367,6 +373,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
367373
setOperationAction(ISD::LLRINT, MVT::f32, Legal);
368374
setOperationAction(ISD::LROUND, MVT::f32, Legal);
369375
setOperationAction(ISD::LLROUND, MVT::f32, Legal);
376+
setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
377+
setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal);
378+
setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
379+
setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
380+
setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
381+
setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
370382
for (auto CC : FPCCToExpand)
371383
setCondCodeAction(CC, MVT::f32, Expand);
372384
setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
@@ -388,6 +400,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
388400
setOperationAction(ISD::LLRINT, MVT::f64, Legal);
389401
setOperationAction(ISD::LROUND, MVT::f64, Legal);
390402
setOperationAction(ISD::LLROUND, MVT::f64, Legal);
403+
setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal);
404+
setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
405+
setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
406+
setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
407+
setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
408+
setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
391409
for (auto CC : FPCCToExpand)
392410
setCondCodeAction(CC, MVT::f64, Expand);
393411
setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);

‎llvm/lib/Target/RISCV/RISCVInstrInfoD.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -192,12 +192,12 @@ def : Pat<(fpextend FPR32:$rs1), (FCVT_D_S FPR32:$rs1)>;
192192

193193
/// Float arithmetic operations
194194

195-
def : PatFpr64Fpr64DynFrm<fadd, FADD_D>;
196-
def : PatFpr64Fpr64DynFrm<fsub, FSUB_D>;
197-
def : PatFpr64Fpr64DynFrm<fmul, FMUL_D>;
198-
def : PatFpr64Fpr64DynFrm<fdiv, FDIV_D>;
195+
def : PatFpr64Fpr64DynFrm<any_fadd, FADD_D>;
196+
def : PatFpr64Fpr64DynFrm<any_fsub, FSUB_D>;
197+
def : PatFpr64Fpr64DynFrm<any_fmul, FMUL_D>;
198+
def : PatFpr64Fpr64DynFrm<any_fdiv, FDIV_D>;
199199

200-
def : Pat<(fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
200+
def : Pat<(any_fsqrt FPR64:$rs1), (FSQRT_D FPR64:$rs1, 0b111)>;
201201

202202
def : Pat<(fneg FPR64:$rs1), (FSGNJN_D $rs1, $rs1)>;
203203
def : Pat<(fabs FPR64:$rs1), (FSGNJX_D $rs1, $rs1)>;
@@ -209,19 +209,19 @@ def : Pat<(fcopysign FPR32:$rs1, FPR64:$rs2), (FSGNJ_S $rs1, (FCVT_S_D $rs2,
209209
0b111))>;
210210

211211
// fmadd: rs1 * rs2 + rs3
212-
def : Pat<(fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
212+
def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, FPR64:$rs3),
213213
(FMADD_D $rs1, $rs2, $rs3, 0b111)>;
214214

215215
// fmsub: rs1 * rs2 - rs3
216-
def : Pat<(fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
216+
def : Pat<(any_fma FPR64:$rs1, FPR64:$rs2, (fneg FPR64:$rs3)),
217217
(FMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
218218

219219
// fnmsub: -rs1 * rs2 + rs3
220-
def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
220+
def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
221221
(FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
222222

223223
// fnmadd: -rs1 * rs2 - rs3
224-
def : Pat<(fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
224+
def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
225225
(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
226226

227227
// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches

‎llvm/lib/Target/RISCV/RISCVInstrInfoF.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -313,12 +313,12 @@ def : Pat<(f32 (fpimm0)), (FMV_W_X X0)>;
313313

314314
/// Float arithmetic operations
315315

316-
def : PatFpr32Fpr32DynFrm<fadd, FADD_S>;
317-
def : PatFpr32Fpr32DynFrm<fsub, FSUB_S>;
318-
def : PatFpr32Fpr32DynFrm<fmul, FMUL_S>;
319-
def : PatFpr32Fpr32DynFrm<fdiv, FDIV_S>;
316+
def : PatFpr32Fpr32DynFrm<any_fadd, FADD_S>;
317+
def : PatFpr32Fpr32DynFrm<any_fsub, FSUB_S>;
318+
def : PatFpr32Fpr32DynFrm<any_fmul, FMUL_S>;
319+
def : PatFpr32Fpr32DynFrm<any_fdiv, FDIV_S>;
320320

321-
def : Pat<(fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
321+
def : Pat<(any_fsqrt FPR32:$rs1), (FSQRT_S FPR32:$rs1, 0b111)>;
322322

323323
def : Pat<(fneg FPR32:$rs1), (FSGNJN_S $rs1, $rs1)>;
324324
def : Pat<(fabs FPR32:$rs1), (FSGNJX_S $rs1, $rs1)>;
@@ -327,19 +327,19 @@ def : PatFpr32Fpr32<fcopysign, FSGNJ_S>;
327327
def : Pat<(fcopysign FPR32:$rs1, (fneg FPR32:$rs2)), (FSGNJN_S $rs1, $rs2)>;
328328

329329
// fmadd: rs1 * rs2 + rs3
330-
def : Pat<(fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3),
330+
def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, FPR32:$rs3),
331331
(FMADD_S $rs1, $rs2, $rs3, 0b111)>;
332332

333333
// fmsub: rs1 * rs2 - rs3
334-
def : Pat<(fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
334+
def : Pat<(any_fma FPR32:$rs1, FPR32:$rs2, (fneg FPR32:$rs3)),
335335
(FMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
336336

337337
// fnmsub: -rs1 * rs2 + rs3
338-
def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
338+
def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
339339
(FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
340340

341341
// fnmadd: -rs1 * rs2 - rs3
342-
def : Pat<(fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
342+
def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
343343
(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
344344

345345
// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches

‎llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -215,12 +215,12 @@ def : Pat<(f16 (fpimm0)), (FMV_H_X X0)>;
215215

216216
/// Float arithmetic operations
217217

218-
def : PatFpr16Fpr16DynFrm<fadd, FADD_H>;
219-
def : PatFpr16Fpr16DynFrm<fsub, FSUB_H>;
220-
def : PatFpr16Fpr16DynFrm<fmul, FMUL_H>;
221-
def : PatFpr16Fpr16DynFrm<fdiv, FDIV_H>;
218+
def : PatFpr16Fpr16DynFrm<any_fadd, FADD_H>;
219+
def : PatFpr16Fpr16DynFrm<any_fsub, FSUB_H>;
220+
def : PatFpr16Fpr16DynFrm<any_fmul, FMUL_H>;
221+
def : PatFpr16Fpr16DynFrm<any_fdiv, FDIV_H>;
222222

223-
def : Pat<(fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>;
223+
def : Pat<(any_fsqrt FPR16:$rs1), (FSQRT_H FPR16:$rs1, 0b111)>;
224224

225225
def : Pat<(fneg FPR16:$rs1), (FSGNJN_H $rs1, $rs1)>;
226226
def : Pat<(fabs FPR16:$rs1), (FSGNJX_H $rs1, $rs1)>;
@@ -232,19 +232,19 @@ def : Pat<(fcopysign FPR16:$rs1, FPR32:$rs2),
232232
def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>;
233233

234234
// fmadd: rs1 * rs2 + rs3
235-
def : Pat<(fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3),
235+
def : Pat<(any_fma FPR16:$rs1, FPR16:$rs2, FPR16:$rs3),
236236
(FMADD_H $rs1, $rs2, $rs3, 0b111)>;
237237

238238
// fmsub: rs1 * rs2 - rs3
239-
def : Pat<(fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3)),
239+
def : Pat<(any_fma FPR16:$rs1, FPR16:$rs2, (fneg FPR16:$rs3)),
240240
(FMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
241241

242242
// fnmsub: -rs1 * rs2 + rs3
243-
def : Pat<(fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3),
243+
def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3),
244244
(FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
245245

246246
// fnmadd: -rs1 * rs2 - rs3
247-
def : Pat<(fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)),
247+
def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)),
248248
(FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
249249

250250
// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches

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