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[RISCV][GISel] Support nxv16p0 for RV32. (#101573)
Pointers are 32 bits on RV32 so nxv1p0 is lmul=mf2 and nxv16p0 is lmul=m8. Split the test so we can have different alignments and register class sizes for rv32 and rv64 for the pointer tests.
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7 files changed

+283
-146
lines changed

7 files changed

+283
-146
lines changed

‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,9 @@ static LegalityPredicate typeIsLegalPtrVec(unsigned TypeIdx,
7474
LegalityPredicate P = [=, &ST](const LegalityQuery &Query) {
7575
return ST.hasVInstructions() &&
7676
(Query.Types[TypeIdx].getElementCount().getKnownMinValue() != 1 ||
77-
ST.getELen() == 64);
77+
ST.getELen() == 64) &&
78+
(Query.Types[TypeIdx].getElementCount().getKnownMinValue() != 16 ||
79+
Query.Types[TypeIdx].getScalarSizeInBits() == 32);
7880
};
7981
return all(typeInSet(TypeIdx, PtrVecTys), P);
8082
}
@@ -127,6 +129,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
127129
const LLT nxv2p0 = LLT::scalable_vector(2, p0);
128130
const LLT nxv4p0 = LLT::scalable_vector(4, p0);
129131
const LLT nxv8p0 = LLT::scalable_vector(8, p0);
132+
const LLT nxv16p0 = LLT::scalable_vector(16, p0);
130133

131134
using namespace TargetOpcode;
132135

@@ -137,7 +140,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
137140
nxv32s16, nxv1s32, nxv2s32, nxv4s32, nxv8s32, nxv16s32,
138141
nxv1s64, nxv2s64, nxv4s64, nxv8s64};
139142

140-
auto PtrVecTys = {nxv1p0, nxv2p0, nxv4p0, nxv8p0};
143+
auto PtrVecTys = {nxv1p0, nxv2p0, nxv4p0, nxv8p0, nxv16p0};
141144

142145
getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
143146
.legalFor({s32, sXLen})

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv32.mir

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: vload_nxv1ptr
6+
body: |
7+
bb.1:
8+
liveins: $x10
9+
10+
; CHECK-LABEL: name: vload_nxv1ptr
11+
; CHECK: liveins: $x10
12+
; CHECK-NEXT: {{ $}}
13+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
14+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>))
15+
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)
16+
; CHECK-NEXT: PseudoRET implicit $v8
17+
%0:_(p0) = COPY $x10
18+
%1:_(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>), align 4)
19+
$v8 = COPY %1(<vscale x 1 x p0>)
20+
PseudoRET implicit $v8
21+
22+
...
23+
---
24+
name: vload_nxv2ptr
25+
body: |
26+
bb.1:
27+
liveins: $x10
28+
29+
; CHECK-LABEL: name: vload_nxv2ptr
30+
; CHECK: liveins: $x10
31+
; CHECK-NEXT: {{ $}}
32+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
33+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>))
34+
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x p0>)
35+
; CHECK-NEXT: PseudoRET implicit $v8
36+
%0:_(p0) = COPY $x10
37+
%1:_(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>), align 8)
38+
$v8 = COPY %1(<vscale x 2 x p0>)
39+
PseudoRET implicit $v8
40+
41+
...
42+
---
43+
name: vload_nxv8ptr
44+
body: |
45+
bb.1:
46+
liveins: $x10
47+
48+
; CHECK-LABEL: name: vload_nxv8ptr
49+
; CHECK: liveins: $x10
50+
; CHECK-NEXT: {{ $}}
51+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
52+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>))
53+
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x p0>)
54+
; CHECK-NEXT: PseudoRET implicit $v8m4
55+
%0:_(p0) = COPY $x10
56+
%1:_(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>), align 32)
57+
$v8m4 = COPY %1(<vscale x 8 x p0>)
58+
PseudoRET implicit $v8m4
59+
60+
...
61+
---
62+
name: vload_nxv16ptr
63+
body: |
64+
bb.1:
65+
liveins: $x10
66+
67+
; CHECK-LABEL: name: vload_nxv16ptr
68+
; CHECK: liveins: $x10
69+
; CHECK-NEXT: {{ $}}
70+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
71+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 16 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 16 x p0>))
72+
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 16 x p0>)
73+
; CHECK-NEXT: PseudoRET implicit $v8m8
74+
%0:_(p0) = COPY $x10
75+
%1:_(<vscale x 16 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 16 x p0>), align 64)
76+
$v8m4 = COPY %1(<vscale x 16 x p0>)
77+
PseudoRET implicit $v8m8
78+
79+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load-rv64.mir

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: vload_nxv1ptr
6+
body: |
7+
bb.1:
8+
liveins: $x10
9+
10+
; CHECK-LABEL: name: vload_nxv1ptr
11+
; CHECK: liveins: $x10
12+
; CHECK-NEXT: {{ $}}
13+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
14+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>))
15+
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)
16+
; CHECK-NEXT: PseudoRET implicit $v8
17+
%0:_(p0) = COPY $x10
18+
%1:_(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>), align 8)
19+
$v8 = COPY %1(<vscale x 1 x p0>)
20+
PseudoRET implicit $v8
21+
22+
...
23+
---
24+
name: vload_nxv2ptr
25+
body: |
26+
bb.1:
27+
liveins: $x10
28+
29+
; CHECK-LABEL: name: vload_nxv2ptr
30+
; CHECK: liveins: $x10
31+
; CHECK-NEXT: {{ $}}
32+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
33+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>))
34+
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x p0>)
35+
; CHECK-NEXT: PseudoRET implicit $v8m2
36+
%0:_(p0) = COPY $x10
37+
%1:_(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>), align 16)
38+
$v8 = COPY %1(<vscale x 2 x p0>)
39+
PseudoRET implicit $v8m2
40+
41+
...
42+
---
43+
name: vload_nxv8ptr
44+
body: |
45+
bb.1:
46+
liveins: $x10
47+
48+
; CHECK-LABEL: name: vload_nxv8ptr
49+
; CHECK: liveins: $x10
50+
; CHECK-NEXT: {{ $}}
51+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
52+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>))
53+
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x p0>)
54+
; CHECK-NEXT: PseudoRET implicit $v8m8
55+
%0:_(p0) = COPY $x10
56+
%1:_(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>), align 64)
57+
$v8m4 = COPY %1(<vscale x 8 x p0>)
58+
PseudoRET implicit $v8m8
59+
60+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-load.mir

Lines changed: 0 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -203,21 +203,6 @@
203203
ret <vscale x 2 x i64> %va
204204
}
205205

206-
define <vscale x 1 x ptr> @vload_nxv1ptr(ptr %pa) #0 {
207-
%va = load <vscale x 1 x ptr>, ptr %pa, align 4
208-
ret <vscale x 1 x ptr> %va
209-
}
210-
211-
define <vscale x 2 x ptr> @vload_nxv2ptr(ptr %pa) #0 {
212-
%va = load <vscale x 2 x ptr>, ptr %pa, align 8
213-
ret <vscale x 2 x ptr> %va
214-
}
215-
216-
define <vscale x 8 x ptr> @vload_nxv8ptr(ptr %pa) #0 {
217-
%va = load <vscale x 8 x ptr>, ptr %pa, align 32
218-
ret <vscale x 8 x ptr> %va
219-
}
220-
221206
attributes #0 = { "target-features"="+v" }
222207

223208
...
@@ -984,60 +969,3 @@ body: |
984969
PseudoRET implicit $v8m2
985970
986971
...
987-
---
988-
name: vload_nxv1ptr
989-
body: |
990-
bb.1 (%ir-block.0):
991-
liveins: $x10
992-
993-
; CHECK-LABEL: name: vload_nxv1ptr
994-
; CHECK: liveins: $x10
995-
; CHECK-NEXT: {{ $}}
996-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
997-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 1 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 1 x p0>) from %ir.pa)
998-
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 1 x p0>)
999-
; CHECK-NEXT: PseudoRET implicit $v8
1000-
%0:_(p0) = COPY $x10
1001-
%1:_(<vscale x 1 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 1 x p0>) from %ir.pa)
1002-
$v8 = COPY %1(<vscale x 1 x p0>)
1003-
PseudoRET implicit $v8
1004-
1005-
...
1006-
---
1007-
name: vload_nxv2ptr
1008-
body: |
1009-
bb.1 (%ir-block.0):
1010-
liveins: $x10
1011-
1012-
; CHECK-LABEL: name: vload_nxv2ptr
1013-
; CHECK: liveins: $x10
1014-
; CHECK-NEXT: {{ $}}
1015-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
1016-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 2 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 2 x p0>) from %ir.pa)
1017-
; CHECK-NEXT: $v8 = COPY [[LOAD]](<vscale x 2 x p0>)
1018-
; CHECK-NEXT: PseudoRET implicit $v8
1019-
%0:_(p0) = COPY $x10
1020-
%1:_(<vscale x 2 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 2 x p0>) from %ir.pa)
1021-
$v8 = COPY %1(<vscale x 2 x p0>)
1022-
PseudoRET implicit $v8
1023-
1024-
...
1025-
---
1026-
name: vload_nxv8ptr
1027-
body: |
1028-
bb.1 (%ir-block.0):
1029-
liveins: $x10
1030-
1031-
; CHECK-LABEL: name: vload_nxv8ptr
1032-
; CHECK: liveins: $x10
1033-
; CHECK-NEXT: {{ $}}
1034-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
1035-
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<vscale x 8 x p0>) = G_LOAD [[COPY]](p0) :: (load (<vscale x 8 x p0>) from %ir.pa)
1036-
; CHECK-NEXT: $v8m4 = COPY [[LOAD]](<vscale x 8 x p0>)
1037-
; CHECK-NEXT: PseudoRET implicit $v8m4
1038-
%0:_(p0) = COPY $x10
1039-
%1:_(<vscale x 8 x p0>) = G_LOAD %0(p0) :: (load (<vscale x 8 x p0>) from %ir.pa)
1040-
$v8m4 = COPY %1(<vscale x 8 x p0>)
1041-
PseudoRET implicit $v8m4
1042-
1043-
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv32.mir

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv32 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: vstore_nx1ptr
6+
body: |
7+
bb.1:
8+
liveins: $v8, $x10
9+
10+
; CHECK-LABEL: name: vstore_nx1ptr
11+
; CHECK: liveins: $v8, $x10
12+
; CHECK-NEXT: {{ $}}
13+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
14+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x p0>) = COPY $v8
15+
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 1 x p0>), [[COPY]](p0) :: (store (<vscale x 1 x p0>))
16+
; CHECK-NEXT: PseudoRET
17+
%0:_(p0) = COPY $x10
18+
%1:_(<vscale x 1 x p0>) = COPY $v8
19+
G_STORE %1(<vscale x 1 x p0>), %0(p0) :: (store (<vscale x 1 x p0>), align 4)
20+
PseudoRET
21+
22+
...
23+
---
24+
name: vstore_nx2ptr
25+
body: |
26+
bb.1:
27+
liveins: $x10, $v8
28+
29+
; CHECK-LABEL: name: vstore_nx2ptr
30+
; CHECK: liveins: $x10, $v8
31+
; CHECK-NEXT: {{ $}}
32+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
33+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x p0>) = COPY $v8
34+
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 2 x p0>), [[COPY]](p0) :: (store (<vscale x 2 x p0>))
35+
; CHECK-NEXT: PseudoRET
36+
%0:_(p0) = COPY $x10
37+
%1:_(<vscale x 2 x p0>) = COPY $v8
38+
G_STORE %1(<vscale x 2 x p0>), %0(p0) :: (store (<vscale x 2 x p0>), align 8)
39+
PseudoRET
40+
41+
...
42+
---
43+
name: vstore_nx8ptr
44+
body: |
45+
bb.1:
46+
liveins: $x10, $v8m4
47+
48+
; CHECK-LABEL: name: vstore_nx8ptr
49+
; CHECK: liveins: $x10, $v8m4
50+
; CHECK-NEXT: {{ $}}
51+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
52+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x p0>) = COPY $v8m4
53+
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 8 x p0>), [[COPY]](p0) :: (store (<vscale x 8 x p0>))
54+
; CHECK-NEXT: PseudoRET
55+
%0:_(p0) = COPY $x10
56+
%1:_(<vscale x 8 x p0>) = COPY $v8m4
57+
G_STORE %1(<vscale x 8 x p0>), %0(p0) :: (store (<vscale x 8 x p0>), align 32)
58+
PseudoRET
59+
60+
...
61+
---
62+
name: vstore_nx16ptr
63+
body: |
64+
bb.1:
65+
liveins: $x10, $v8m8
66+
67+
; CHECK-LABEL: name: vstore_nx16ptr
68+
; CHECK: liveins: $x10, $v8m8
69+
; CHECK-NEXT: {{ $}}
70+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
71+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 16 x p0>) = COPY $v8m8
72+
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 16 x p0>), [[COPY]](p0) :: (store (<vscale x 8 x p0>), align 64)
73+
; CHECK-NEXT: PseudoRET
74+
%0:_(p0) = COPY $x10
75+
%1:_(<vscale x 16 x p0>) = COPY $v8m8
76+
G_STORE %1(<vscale x 16 x p0>), %0(p0) :: (store (<vscale x 8 x p0>), align 64)
77+
PseudoRET
78+
79+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rvv/legalize-store-rv64.mir

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -mtriple=riscv64 -mattr=+v -run-pass=legalizer %s -o - | FileCheck %s
3+
4+
---
5+
name: vstore_nx1ptr
6+
body: |
7+
bb.1:
8+
liveins: $v8, $x10
9+
10+
; CHECK-LABEL: name: vstore_nx1ptr
11+
; CHECK: liveins: $v8, $x10
12+
; CHECK-NEXT: {{ $}}
13+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
14+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 1 x p0>) = COPY $v8
15+
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 1 x p0>), [[COPY]](p0) :: (store (<vscale x 1 x p0>))
16+
; CHECK-NEXT: PseudoRET
17+
%0:_(p0) = COPY $x10
18+
%1:_(<vscale x 1 x p0>) = COPY $v8
19+
G_STORE %1(<vscale x 1 x p0>), %0(p0) :: (store (<vscale x 1 x p0>), align 8)
20+
PseudoRET
21+
22+
...
23+
---
24+
name: vstore_nx2ptr
25+
body: |
26+
bb.1:
27+
liveins: $x10, $v8m2
28+
29+
; CHECK-LABEL: name: vstore_nx2ptr
30+
; CHECK: liveins: $x10, $v8m2
31+
; CHECK-NEXT: {{ $}}
32+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
33+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 2 x p0>) = COPY $v8m2
34+
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 2 x p0>), [[COPY]](p0) :: (store (<vscale x 2 x p0>))
35+
; CHECK-NEXT: PseudoRET
36+
%0:_(p0) = COPY $x10
37+
%1:_(<vscale x 2 x p0>) = COPY $v8m2
38+
G_STORE %1(<vscale x 2 x p0>), %0(p0) :: (store (<vscale x 2 x p0>), align 16)
39+
PseudoRET
40+
41+
...
42+
---
43+
name: vstore_nx8ptr
44+
body: |
45+
bb.1:
46+
liveins: $x10, $v8m8
47+
48+
; CHECK-LABEL: name: vstore_nx8ptr
49+
; CHECK: liveins: $x10, $v8m8
50+
; CHECK-NEXT: {{ $}}
51+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
52+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<vscale x 8 x p0>) = COPY $v8m8
53+
; CHECK-NEXT: G_STORE [[COPY1]](<vscale x 8 x p0>), [[COPY]](p0) :: (store (<vscale x 8 x p0>))
54+
; CHECK-NEXT: PseudoRET
55+
%0:_(p0) = COPY $x10
56+
%1:_(<vscale x 8 x p0>) = COPY $v8m8
57+
G_STORE %1(<vscale x 8 x p0>), %0(p0) :: (store (<vscale x 8 x p0>), align 64)
58+
PseudoRET
59+
60+
...

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