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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 |
| 2 | +; Test basic address sanitizer instrumentation. |
| 3 | +; |
| 4 | +; RUN: opt < %s -passes=hwasan -hwasan-mapping-offset=4398046511104 -S | FileCheck %s |
| 5 | + |
| 6 | + |
| 7 | +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" |
| 8 | +target triple = "aarch64--linux-android9001" |
| 9 | + |
| 10 | +define i8 @test_load8(ptr %a) sanitize_hwaddress { |
| 11 | +; CHECK-LABEL: define i8 @test_load8 |
| 12 | +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] { |
| 13 | +; CHECK-NEXT: entry: |
| 14 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 15 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 0) |
| 16 | +; CHECK-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4 |
| 17 | +; CHECK-NEXT: ret i8 [[B]] |
| 18 | +; |
| 19 | +entry: |
| 20 | + %b = load i8, ptr %a, align 4 |
| 21 | + ret i8 %b |
| 22 | +} |
| 23 | + |
| 24 | +define i16 @test_load16(ptr %a) sanitize_hwaddress { |
| 25 | +; CHECK-LABEL: define i16 @test_load16 |
| 26 | +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { |
| 27 | +; CHECK-NEXT: entry: |
| 28 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 29 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 1) |
| 30 | +; CHECK-NEXT: [[B:%.*]] = load i16, ptr [[A]], align 4 |
| 31 | +; CHECK-NEXT: ret i16 [[B]] |
| 32 | +; |
| 33 | +entry: |
| 34 | + %b = load i16, ptr %a, align 4 |
| 35 | + ret i16 %b |
| 36 | +} |
| 37 | + |
| 38 | +define i32 @test_load32(ptr %a) sanitize_hwaddress { |
| 39 | +; CHECK-LABEL: define i32 @test_load32 |
| 40 | +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { |
| 41 | +; CHECK-NEXT: entry: |
| 42 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 43 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 2) |
| 44 | +; CHECK-NEXT: [[B:%.*]] = load i32, ptr [[A]], align 4 |
| 45 | +; CHECK-NEXT: ret i32 [[B]] |
| 46 | +; |
| 47 | +entry: |
| 48 | + %b = load i32, ptr %a, align 4 |
| 49 | + ret i32 %b |
| 50 | +} |
| 51 | + |
| 52 | +define i64 @test_load64(ptr %a) sanitize_hwaddress { |
| 53 | +; CHECK-LABEL: define i64 @test_load64 |
| 54 | +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { |
| 55 | +; CHECK-NEXT: entry: |
| 56 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 57 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 3) |
| 58 | +; CHECK-NEXT: [[B:%.*]] = load i64, ptr [[A]], align 8 |
| 59 | +; CHECK-NEXT: ret i64 [[B]] |
| 60 | +; |
| 61 | +entry: |
| 62 | + %b = load i64, ptr %a, align 8 |
| 63 | + ret i64 %b |
| 64 | +} |
| 65 | + |
| 66 | +define i128 @test_load128(ptr %a) sanitize_hwaddress { |
| 67 | +; CHECK-LABEL: define i128 @test_load128 |
| 68 | +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { |
| 69 | +; CHECK-NEXT: entry: |
| 70 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 71 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 4) |
| 72 | +; CHECK-NEXT: [[B:%.*]] = load i128, ptr [[A]], align 16 |
| 73 | +; CHECK-NEXT: ret i128 [[B]] |
| 74 | +; |
| 75 | +entry: |
| 76 | + %b = load i128, ptr %a, align 16 |
| 77 | + ret i128 %b |
| 78 | +} |
| 79 | + |
| 80 | +define i40 @test_load40(ptr %a) sanitize_hwaddress { |
| 81 | +; CHECK-LABEL: define i40 @test_load40 |
| 82 | +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { |
| 83 | +; CHECK-NEXT: entry: |
| 84 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 85 | +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64 |
| 86 | +; CHECK-NEXT: call void @__hwasan_loadN(i64 [[TMP0]], i64 5) |
| 87 | +; CHECK-NEXT: [[B:%.*]] = load i40, ptr [[A]], align 4 |
| 88 | +; CHECK-NEXT: ret i40 [[B]] |
| 89 | +; |
| 90 | +entry: |
| 91 | + %b = load i40, ptr %a, align 4 |
| 92 | + ret i40 %b |
| 93 | +} |
| 94 | + |
| 95 | +define void @test_store8(ptr %a, i8 %b) sanitize_hwaddress { |
| 96 | +; CHECK-LABEL: define void @test_store8 |
| 97 | +; CHECK-SAME: (ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { |
| 98 | +; CHECK-NEXT: entry: |
| 99 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 100 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 16) |
| 101 | +; CHECK-NEXT: store i8 [[B]], ptr [[A]], align 4 |
| 102 | +; CHECK-NEXT: ret void |
| 103 | +; |
| 104 | +entry: |
| 105 | + store i8 %b, ptr %a, align 4 |
| 106 | + ret void |
| 107 | +} |
| 108 | + |
| 109 | +define void @test_store16(ptr %a, i16 %b) sanitize_hwaddress { |
| 110 | +; CHECK-LABEL: define void @test_store16 |
| 111 | +; CHECK-SAME: (ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { |
| 112 | +; CHECK-NEXT: entry: |
| 113 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 114 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 17) |
| 115 | +; CHECK-NEXT: store i16 [[B]], ptr [[A]], align 4 |
| 116 | +; CHECK-NEXT: ret void |
| 117 | +; |
| 118 | +entry: |
| 119 | + store i16 %b, ptr %a, align 4 |
| 120 | + ret void |
| 121 | +} |
| 122 | + |
| 123 | +define void @test_store32(ptr %a, i32 %b) sanitize_hwaddress { |
| 124 | +; CHECK-LABEL: define void @test_store32 |
| 125 | +; CHECK-SAME: (ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { |
| 126 | +; CHECK-NEXT: entry: |
| 127 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 128 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 18) |
| 129 | +; CHECK-NEXT: store i32 [[B]], ptr [[A]], align 4 |
| 130 | +; CHECK-NEXT: ret void |
| 131 | +; |
| 132 | +entry: |
| 133 | + store i32 %b, ptr %a, align 4 |
| 134 | + ret void |
| 135 | +} |
| 136 | + |
| 137 | +define void @test_store64(ptr %a, i64 %b) sanitize_hwaddress { |
| 138 | +; CHECK-LABEL: define void @test_store64 |
| 139 | +; CHECK-SAME: (ptr [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| 140 | +; CHECK-NEXT: entry: |
| 141 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 142 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 19) |
| 143 | +; CHECK-NEXT: store i64 [[B]], ptr [[A]], align 8 |
| 144 | +; CHECK-NEXT: ret void |
| 145 | +; |
| 146 | +entry: |
| 147 | + store i64 %b, ptr %a, align 8 |
| 148 | + ret void |
| 149 | +} |
| 150 | + |
| 151 | +define void @test_store128(ptr %a, i128 %b) sanitize_hwaddress { |
| 152 | +; CHECK-LABEL: define void @test_store128 |
| 153 | +; CHECK-SAME: (ptr [[A:%.*]], i128 [[B:%.*]]) #[[ATTR0]] { |
| 154 | +; CHECK-NEXT: entry: |
| 155 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 156 | +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 20) |
| 157 | +; CHECK-NEXT: store i128 [[B]], ptr [[A]], align 16 |
| 158 | +; CHECK-NEXT: ret void |
| 159 | +; |
| 160 | +entry: |
| 161 | + store i128 %b, ptr %a, align 16 |
| 162 | + ret void |
| 163 | +} |
| 164 | + |
| 165 | +define void @test_store40(ptr %a, i40 %b) sanitize_hwaddress { |
| 166 | +; CHECK-LABEL: define void @test_store40 |
| 167 | +; CHECK-SAME: (ptr [[A:%.*]], i40 [[B:%.*]]) #[[ATTR0]] { |
| 168 | +; CHECK-NEXT: entry: |
| 169 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 170 | +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64 |
| 171 | +; CHECK-NEXT: call void @__hwasan_storeN(i64 [[TMP0]], i64 5) |
| 172 | +; CHECK-NEXT: store i40 [[B]], ptr [[A]], align 4 |
| 173 | +; CHECK-NEXT: ret void |
| 174 | +; |
| 175 | +entry: |
| 176 | + store i40 %b, ptr %a, align 4 |
| 177 | + ret void |
| 178 | +} |
| 179 | + |
| 180 | +define void @test_store_unaligned(ptr %a, i64 %b) sanitize_hwaddress { |
| 181 | +; CHECK-LABEL: define void @test_store_unaligned |
| 182 | +; CHECK-SAME: (ptr [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { |
| 183 | +; CHECK-NEXT: entry: |
| 184 | +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) |
| 185 | +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64 |
| 186 | +; CHECK-NEXT: call void @__hwasan_storeN(i64 [[TMP0]], i64 8) |
| 187 | +; CHECK-NEXT: store i64 [[B]], ptr [[A]], align 4 |
| 188 | +; CHECK-NEXT: ret void |
| 189 | +; |
| 190 | +entry: |
| 191 | + store i64 %b, ptr %a, align 4 |
| 192 | + ret void |
| 193 | +} |
| 194 | + |
| 195 | +define i8 @test_load_noattr(ptr %a) { |
| 196 | +; CHECK-LABEL: define i8 @test_load_noattr |
| 197 | +; CHECK-SAME: (ptr [[A:%.*]]) { |
| 198 | +; CHECK-NEXT: entry: |
| 199 | +; CHECK-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4 |
| 200 | +; CHECK-NEXT: ret i8 [[B]] |
| 201 | +; |
| 202 | +entry: |
| 203 | + %b = load i8, ptr %a, align 4 |
| 204 | + ret i8 %b |
| 205 | +} |
| 206 | + |
| 207 | +define i8 @test_load_notmyattr(ptr %a) sanitize_address { |
| 208 | +; CHECK-LABEL: define i8 @test_load_notmyattr |
| 209 | +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR1:[0-9]+]] { |
| 210 | +; CHECK-NEXT: entry: |
| 211 | +; CHECK-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4 |
| 212 | +; CHECK-NEXT: ret i8 [[B]] |
| 213 | +; |
| 214 | +entry: |
| 215 | + %b = load i8, ptr %a, align 4 |
| 216 | + ret i8 %b |
| 217 | +} |
| 218 | + |
| 219 | +define i8 @test_load_addrspace(ptr addrspace(256) %a) sanitize_hwaddress { |
| 220 | +; CHECK-LABEL: define i8 @test_load_addrspace |
| 221 | +; CHECK-SAME: (ptr addrspace(256) [[A:%.*]]) #[[ATTR0]] { |
| 222 | +; CHECK-NEXT: entry: |
| 223 | +; CHECK-NEXT: [[B:%.*]] = load i8, ptr addrspace(256) [[A]], align 4 |
| 224 | +; CHECK-NEXT: ret i8 [[B]] |
| 225 | +; |
| 226 | +entry: |
| 227 | + %b = load i8, ptr addrspace(256) %a, align 4 |
| 228 | + ret i8 %b |
| 229 | +} |
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