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define i1 @icmp_eq_basic (i8 %arg ) {
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; CHECK-LABEL: define i1 @icmp_eq_basic
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; CHECK-SAME: (i8 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG]], i8 2)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[ADD]], 5
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[ARG]], 3
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i8 @llvm.uadd.sat.i8 (i8 %arg , i8 2 )
@@ -22,8 +21,7 @@ define i1 @icmp_eq_basic(i8 %arg) {
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define i1 @icmp_ne_basic (i16 %arg ) {
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; CHECK-LABEL: define i1 @icmp_ne_basic
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; CHECK-SAME: (i16 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG]], i16 8)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i16 [[ADD]], 9
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i16 [[ARG]], 1
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i16 @llvm.uadd.sat.i16 (i16 %arg , i16 8 )
@@ -34,8 +32,7 @@ define i1 @icmp_ne_basic(i16 %arg) {
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define i1 @icmp_ule_basic (i32 %arg ) {
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; CHECK-LABEL: define i1 @icmp_ule_basic
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; CHECK-SAME: (i32 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[ARG]], i32 2)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ADD]], 4
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[ARG]], 2
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i32 @llvm.uadd.sat.i32 (i32 %arg , i32 2 )
@@ -46,8 +43,7 @@ define i1 @icmp_ule_basic(i32 %arg) {
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define i1 @icmp_ult_basic (i64 %arg ) {
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; CHECK-LABEL: define i1 @icmp_ult_basic
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; CHECK-SAME: (i64 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[ARG]], i64 5)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[ADD]], 20
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[ARG]], 15
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i64 @llvm.uadd.sat.i64 (i64 %arg , i64 5 )
@@ -58,8 +54,7 @@ define i1 @icmp_ult_basic(i64 %arg) {
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define i1 @icmp_uge_basic (i8 %arg ) {
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; CHECK-LABEL: define i1 @icmp_uge_basic
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; CHECK-SAME: (i8 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG]], i8 4)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[ADD]], 7
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[ARG]], 3
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i8 @llvm.uadd.sat.i8 (i8 %arg , i8 4 )
@@ -70,8 +65,7 @@ define i1 @icmp_uge_basic(i8 %arg) {
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define i1 @icmp_ugt_basic (i16 %arg ) {
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; CHECK-LABEL: define i1 @icmp_ugt_basic
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; CHECK-SAME: (i16 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG]], i16 1)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i16 [[ADD]], 3
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i16 [[ARG]], 2
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i16 @llvm.uadd.sat.i16 (i16 %arg , i16 1 )
@@ -82,8 +76,7 @@ define i1 @icmp_ugt_basic(i16 %arg) {
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define i1 @icmp_sle_basic (i32 %arg ) {
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; CHECK-LABEL: define i1 @icmp_sle_basic
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; CHECK-SAME: (i32 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call i32 @llvm.uadd.sat.i32(i32 [[ARG]], i32 10)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[ADD]], 9
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[ARG]], 2147483637
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i32 @llvm.uadd.sat.i32 (i32 %arg , i32 10 )
@@ -94,8 +87,7 @@ define i1 @icmp_sle_basic(i32 %arg) {
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define i1 @icmp_slt_basic (i64 %arg ) {
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; CHECK-LABEL: define i1 @icmp_slt_basic
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; CHECK-SAME: (i64 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call i64 @llvm.uadd.sat.i64(i64 [[ARG]], i64 24)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i64 [[ADD]], 5
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i64 [[ARG]], 9223372036854775783
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i64 @llvm.uadd.sat.i64 (i64 %arg , i64 24 )
@@ -106,8 +98,8 @@ define i1 @icmp_slt_basic(i64 %arg) {
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define i1 @icmp_sge_basic (i8 %arg ) {
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; CHECK-LABEL: define i1 @icmp_sge_basic
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; CHECK-SAME: (i8 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD :%.*]] = call i8 @llvm.uadd.sat.i8(i8 [[ARG]], i8 1)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i8 [[ADD ]], 3
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+ ; CHECK-NEXT: [[TMP1 :%.*]] = add i8 [[ARG]], -3
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[TMP1 ]], 124
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i8 @llvm.uadd.sat.i8 (i8 %arg , i8 1 )
@@ -118,8 +110,8 @@ define i1 @icmp_sge_basic(i8 %arg) {
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define i1 @icmp_sgt_basic (i16 %arg ) {
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; CHECK-LABEL: define i1 @icmp_sgt_basic
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; CHECK-SAME: (i16 [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD :%.*]] = call i16 @llvm.uadd.sat.i16(i16 [[ARG]], i16 2)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i16 [[ADD ]], 5
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+ ; CHECK-NEXT: [[TMP1 :%.*]] = add i16 [[ARG]], -4
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i16 [[TMP1 ]], 32762
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; CHECK-NEXT: ret i1 [[CMP]]
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;
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%add = call i16 @llvm.uadd.sat.i16 (i16 %arg , i16 2 )
@@ -150,8 +142,7 @@ define i1 @icmp_eq_multiuse(i8 %arg) {
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define <2 x i1 > @icmp_eq_vector_equal (<2 x i8 > %arg ) {
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; CHECK-LABEL: define <2 x i1> @icmp_eq_vector_equal
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; CHECK-SAME: (<2 x i8> [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> [[ARG]], <2 x i8> <i8 2, i8 2>)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[ADD]], <i8 5, i8 5>
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[ARG]], <i8 3, i8 3>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%add = call <2 x i8 > @llvm.uadd.sat.v2i8 (<2 x i8 > %arg , <2 x i8 > <i8 2 , i8 2 >)
@@ -174,8 +165,7 @@ define <2 x i1> @icmp_eq_vector_unequal(<2 x i8> %arg) {
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define <2 x i1 > @icmp_ne_vector_equal (<2 x i16 > %arg ) {
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; CHECK-LABEL: define <2 x i1> @icmp_ne_vector_equal
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; CHECK-SAME: (<2 x i16> [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> [[ARG]], <2 x i16> <i16 3, i16 3>)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i16> [[ADD]], <i16 5, i16 5>
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i16> [[ARG]], <i16 2, i16 2>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%add = call <2 x i16 > @llvm.uadd.sat.v2i16 (<2 x i16 > %arg , <2 x i16 > <i16 3 , i16 3 >)
@@ -198,8 +188,7 @@ define <2 x i1> @icmp_ne_vector_unequal(<2 x i16> %arg) {
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define <2 x i1 > @icmp_ule_vector_equal (<2 x i32 > %arg ) {
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; CHECK-LABEL: define <2 x i1> @icmp_ule_vector_equal
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; CHECK-SAME: (<2 x i32> [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> [[ARG]], <2 x i32> <i32 3, i32 3>)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[ADD]], <i32 5, i32 5>
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[ARG]], <i32 2, i32 2>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%add = call <2 x i32 > @llvm.uadd.sat.v2i32 (<2 x i32 > %arg , <2 x i32 > <i32 3 , i32 3 >)
@@ -222,8 +211,7 @@ define <2 x i1> @icmp_ule_vector_unequal(<2 x i32> %arg) {
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define <2 x i1 > @icmp_sgt_vector_equal (<2 x i64 > %arg ) {
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; CHECK-LABEL: define <2 x i1> @icmp_sgt_vector_equal
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; CHECK-SAME: (<2 x i64> [[ARG:%.*]]) {
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- ; CHECK-NEXT: [[ADD:%.*]] = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> [[ARG]], <2 x i64> <i64 409623, i64 409623>)
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- ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i64> [[ADD]], <i64 1234, i64 1234>
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+ ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[ARG]], <i64 9223372036854366185, i64 9223372036854366185>
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; CHECK-NEXT: ret <2 x i1> [[CMP]]
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;
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%add = call <2 x i64 > @llvm.uadd.sat.v2i64 (<2 x i64 > %arg , <2 x i64 > <i64 409623 , i64 409623 >)
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