Skip to content

Commit 0ccc1e7

Browse files
vitalybukavitalybuka
committed
Revert "[AArch64] Fold more load.x into load.i with large offset"
Issue #76202 This reverts commit f568763.
1 parent 248fba0 commit 0ccc1e7

File tree

3 files changed

+54
-97
lines changed

3 files changed

+54
-97
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -4094,20 +4094,7 @@ AArch64InstrInfo::getLdStAmountOp(const MachineInstr &MI) {
40944094
switch (MI.getOpcode()) {
40954095
default:
40964096
llvm_unreachable("Unexpected opcode");
4097-
case AArch64::LDRBroX:
40984097
case AArch64::LDRBBroX:
4099-
case AArch64::LDRSBXroX:
4100-
case AArch64::LDRSBWroX:
4101-
case AArch64::LDRHroX:
4102-
case AArch64::LDRHHroX:
4103-
case AArch64::LDRSHXroX:
4104-
case AArch64::LDRSHWroX:
4105-
case AArch64::LDRWroX:
4106-
case AArch64::LDRSroX:
4107-
case AArch64::LDRSWroX:
4108-
case AArch64::LDRDroX:
4109-
case AArch64::LDRXroX:
4110-
case AArch64::LDRQroX:
41114098
return MI.getOperand(4);
41124099
}
41134100
}

‎llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

Lines changed: 3 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -180,7 +180,7 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
180180

181181
// Scan the instruction list to find a register assigned with a const
182182
// value that can be combined with the current instruction (a load or store)
183-
// using base addressing with writeback. Scan backwards.
183+
// using base addressing with writeback. Scan forwards.
184184
MachineBasicBlock::iterator
185185
findMatchingConstOffsetBackward(MachineBasicBlock::iterator I, unsigned Limit,
186186
unsigned &Offset);
@@ -221,7 +221,7 @@ struct AArch64LoadStoreOpt : public MachineFunctionPass {
221221
// Find and merge a base register updates before or after a ld/st instruction.
222222
bool tryToMergeLdStUpdate(MachineBasicBlock::iterator &MBBI);
223223

224-
// Find and merge a index ldr/st instruction into a base ld/st instruction.
224+
// Find and merge a index ldr/st instructions into a base ld/st instruction.
225225
bool tryToMergeIndexLdSt(MachineBasicBlock::iterator &MBBI, int Scale);
226226

227227
bool optimizeBlock(MachineBasicBlock &MBB, bool EnableNarrowZeroStOpt);
@@ -511,34 +511,8 @@ static unsigned getBaseAddressOpcode(unsigned Opc) {
511511
switch (Opc) {
512512
default:
513513
llvm_unreachable("Opcode has no base address equivalent!");
514-
case AArch64::LDRBroX:
515-
return AArch64::LDRBui;
516514
case AArch64::LDRBBroX:
517515
return AArch64::LDRBBui;
518-
case AArch64::LDRSBXroX:
519-
return AArch64::LDRSBXui;
520-
case AArch64::LDRSBWroX:
521-
return AArch64::LDRSBWui;
522-
case AArch64::LDRHroX:
523-
return AArch64::LDRHui;
524-
case AArch64::LDRHHroX:
525-
return AArch64::LDRHHui;
526-
case AArch64::LDRSHXroX:
527-
return AArch64::LDRSHXui;
528-
case AArch64::LDRSHWroX:
529-
return AArch64::LDRSHWui;
530-
case AArch64::LDRWroX:
531-
return AArch64::LDRWui;
532-
case AArch64::LDRSroX:
533-
return AArch64::LDRSui;
534-
case AArch64::LDRSWroX:
535-
return AArch64::LDRSWui;
536-
case AArch64::LDRDroX:
537-
return AArch64::LDRDui;
538-
case AArch64::LDRXroX:
539-
return AArch64::LDRXui;
540-
case AArch64::LDRQroX:
541-
return AArch64::LDRQui;
542516
}
543517
}
544518

@@ -790,31 +764,10 @@ static bool isMergeableIndexLdSt(MachineInstr &MI, int &Scale) {
790764
default:
791765
return false;
792766
// Scaled instructions.
793-
// TODO: Add more index address stores.
794-
case AArch64::LDRBroX:
767+
// TODO: Add more index address loads/stores.
795768
case AArch64::LDRBBroX:
796-
case AArch64::LDRSBXroX:
797-
case AArch64::LDRSBWroX:
798769
Scale = 1;
799770
return true;
800-
case AArch64::LDRHroX:
801-
case AArch64::LDRHHroX:
802-
case AArch64::LDRSHXroX:
803-
case AArch64::LDRSHWroX:
804-
Scale = 2;
805-
return true;
806-
case AArch64::LDRWroX:
807-
case AArch64::LDRSroX:
808-
case AArch64::LDRSWroX:
809-
Scale = 4;
810-
return true;
811-
case AArch64::LDRDroX:
812-
case AArch64::LDRXroX:
813-
Scale = 8;
814-
return true;
815-
case AArch64::LDRQroX:
816-
Scale = 16;
817-
return true;
818771
}
819772
}
820773

‎llvm/test/CodeGen/AArch64/arm64-addrmode.ll

Lines changed: 51 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -239,8 +239,9 @@ define i32 @LdOffset_i8_zext32(ptr %a) {
239239
define i32 @LdOffset_i8_sext32(ptr %a) {
240240
; CHECK-LABEL: LdOffset_i8_sext32:
241241
; CHECK: // %bb.0:
242-
; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
243-
; CHECK-NEXT: ldrsb w0, [x8, #3704]
242+
; CHECK-NEXT: mov w8, #56952 // =0xde78
243+
; CHECK-NEXT: movk w8, #15, lsl #16
244+
; CHECK-NEXT: ldrsb w0, [x0, x8]
244245
; CHECK-NEXT: ret
245246
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
246247
%val = load i8, ptr %arrayidx, align 1
@@ -265,8 +266,9 @@ define i64 @LdOffset_i8_zext64(ptr %a) {
265266
define i64 @LdOffset_i8_sext64(ptr %a) {
266267
; CHECK-LABEL: LdOffset_i8_sext64:
267268
; CHECK: // %bb.0:
268-
; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
269-
; CHECK-NEXT: ldrsb x0, [x8, #3704]
269+
; CHECK-NEXT: mov w8, #56952 // =0xde78
270+
; CHECK-NEXT: movk w8, #15, lsl #16
271+
; CHECK-NEXT: ldrsb x0, [x0, x8]
270272
; CHECK-NEXT: ret
271273
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
272274
%val = load i8, ptr %arrayidx, align 1
@@ -278,8 +280,9 @@ define i64 @LdOffset_i8_sext64(ptr %a) {
278280
define i16 @LdOffset_i16(ptr %a) {
279281
; CHECK-LABEL: LdOffset_i16:
280282
; CHECK: // %bb.0:
281-
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
282-
; CHECK-NEXT: ldrh w0, [x8, #7408]
283+
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
284+
; CHECK-NEXT: movk w8, #31, lsl #16
285+
; CHECK-NEXT: ldrh w0, [x0, x8]
283286
; CHECK-NEXT: ret
284287
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
285288
%val = load i16, ptr %arrayidx, align 2
@@ -290,8 +293,9 @@ define i16 @LdOffset_i16(ptr %a) {
290293
define i32 @LdOffset_i16_zext32(ptr %a) {
291294
; CHECK-LABEL: LdOffset_i16_zext32:
292295
; CHECK: // %bb.0:
293-
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
294-
; CHECK-NEXT: ldrh w0, [x8, #7408]
296+
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
297+
; CHECK-NEXT: movk w8, #31, lsl #16
298+
; CHECK-NEXT: ldrh w0, [x0, x8]
295299
; CHECK-NEXT: ret
296300
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
297301
%val = load i16, ptr %arrayidx, align 2
@@ -303,8 +307,9 @@ define i32 @LdOffset_i16_zext32(ptr %a) {
303307
define i32 @LdOffset_i16_sext32(ptr %a) {
304308
; CHECK-LABEL: LdOffset_i16_sext32:
305309
; CHECK: // %bb.0:
306-
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
307-
; CHECK-NEXT: ldrsh w0, [x8, #7408]
310+
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
311+
; CHECK-NEXT: movk w8, #31, lsl #16
312+
; CHECK-NEXT: ldrsh w0, [x0, x8]
308313
; CHECK-NEXT: ret
309314
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
310315
%val = load i16, ptr %arrayidx, align 2
@@ -316,8 +321,9 @@ define i32 @LdOffset_i16_sext32(ptr %a) {
316321
define i64 @LdOffset_i16_zext64(ptr %a) {
317322
; CHECK-LABEL: LdOffset_i16_zext64:
318323
; CHECK: // %bb.0:
319-
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
320-
; CHECK-NEXT: ldrh w0, [x8, #7408]
324+
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
325+
; CHECK-NEXT: movk w8, #31, lsl #16
326+
; CHECK-NEXT: ldrh w0, [x0, x8]
321327
; CHECK-NEXT: ret
322328
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
323329
%val = load i16, ptr %arrayidx, align 2
@@ -329,8 +335,9 @@ define i64 @LdOffset_i16_zext64(ptr %a) {
329335
define i64 @LdOffset_i16_sext64(ptr %a) {
330336
; CHECK-LABEL: LdOffset_i16_sext64:
331337
; CHECK: // %bb.0:
332-
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
333-
; CHECK-NEXT: ldrsh x0, [x8, #7408]
338+
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
339+
; CHECK-NEXT: movk w8, #31, lsl #16
340+
; CHECK-NEXT: ldrsh x0, [x0, x8]
334341
; CHECK-NEXT: ret
335342
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
336343
%val = load i16, ptr %arrayidx, align 2
@@ -342,8 +349,9 @@ define i64 @LdOffset_i16_sext64(ptr %a) {
342349
define i32 @LdOffset_i32(ptr %a) {
343350
; CHECK-LABEL: LdOffset_i32:
344351
; CHECK: // %bb.0:
345-
; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
346-
; CHECK-NEXT: ldr w0, [x8, #14816]
352+
; CHECK-NEXT: mov w8, #31200 // =0x79e0
353+
; CHECK-NEXT: movk w8, #63, lsl #16
354+
; CHECK-NEXT: ldr w0, [x0, x8]
347355
; CHECK-NEXT: ret
348356
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
349357
%val = load i32, ptr %arrayidx, align 4
@@ -354,8 +362,9 @@ define i32 @LdOffset_i32(ptr %a) {
354362
define i64 @LdOffset_i32_zext64(ptr %a) {
355363
; CHECK-LABEL: LdOffset_i32_zext64:
356364
; CHECK: // %bb.0:
357-
; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
358-
; CHECK-NEXT: ldr w0, [x8, #14816]
365+
; CHECK-NEXT: mov w8, #31200 // =0x79e0
366+
; CHECK-NEXT: movk w8, #63, lsl #16
367+
; CHECK-NEXT: ldr w0, [x0, x8]
359368
; CHECK-NEXT: ret
360369
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
361370
%val = load i32, ptr %arrayidx, align 2
@@ -367,8 +376,9 @@ define i64 @LdOffset_i32_zext64(ptr %a) {
367376
define i64 @LdOffset_i32_sext64(ptr %a) {
368377
; CHECK-LABEL: LdOffset_i32_sext64:
369378
; CHECK: // %bb.0:
370-
; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
371-
; CHECK-NEXT: ldrsw x0, [x8, #14816]
379+
; CHECK-NEXT: mov w8, #31200 // =0x79e0
380+
; CHECK-NEXT: movk w8, #63, lsl #16
381+
; CHECK-NEXT: ldrsw x0, [x0, x8]
372382
; CHECK-NEXT: ret
373383
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
374384
%val = load i32, ptr %arrayidx, align 2
@@ -380,8 +390,9 @@ define i64 @LdOffset_i32_sext64(ptr %a) {
380390
define i64 @LdOffset_i64(ptr %a) {
381391
; CHECK-LABEL: LdOffset_i64:
382392
; CHECK: // %bb.0:
383-
; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
384-
; CHECK-NEXT: ldr x0, [x8, #29632]
393+
; CHECK-NEXT: mov w8, #62400 // =0xf3c0
394+
; CHECK-NEXT: movk w8, #126, lsl #16
395+
; CHECK-NEXT: ldr x0, [x0, x8]
385396
; CHECK-NEXT: ret
386397
%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992
387398
%val = load i64, ptr %arrayidx, align 4
@@ -392,8 +403,9 @@ define i64 @LdOffset_i64(ptr %a) {
392403
define <2 x i32> @LdOffset_v2i32(ptr %a) {
393404
; CHECK-LABEL: LdOffset_v2i32:
394405
; CHECK: // %bb.0:
395-
; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
396-
; CHECK-NEXT: ldr d0, [x8, #29632]
406+
; CHECK-NEXT: mov w8, #62400 // =0xf3c0
407+
; CHECK-NEXT: movk w8, #126, lsl #16
408+
; CHECK-NEXT: ldr d0, [x0, x8]
397409
; CHECK-NEXT: ret
398410
%arrayidx = getelementptr inbounds <2 x i32>, ptr %a, i64 1039992
399411
%val = load <2 x i32>, ptr %arrayidx, align 4
@@ -404,8 +416,9 @@ define <2 x i32> @LdOffset_v2i32(ptr %a) {
404416
define <2 x i64> @LdOffset_v2i64(ptr %a) {
405417
; CHECK-LABEL: LdOffset_v2i64:
406418
; CHECK: // %bb.0:
407-
; CHECK-NEXT: add x8, x0, #4048, lsl #12 // =16580608
408-
; CHECK-NEXT: ldr q0, [x8, #59264]
419+
; CHECK-NEXT: mov w8, #59264 // =0xe780
420+
; CHECK-NEXT: movk w8, #253, lsl #16
421+
; CHECK-NEXT: ldr q0, [x0, x8]
409422
; CHECK-NEXT: ret
410423
%arrayidx = getelementptr inbounds <2 x i64>, ptr %a, i64 1039992
411424
%val = load <2 x i64>, ptr %arrayidx, align 4
@@ -416,8 +429,9 @@ define <2 x i64> @LdOffset_v2i64(ptr %a) {
416429
define double @LdOffset_i8_f64(ptr %a) {
417430
; CHECK-LABEL: LdOffset_i8_f64:
418431
; CHECK: // %bb.0:
419-
; CHECK-NEXT: add x8, x0, #253, lsl #12 // =1036288
420-
; CHECK-NEXT: ldrsb w8, [x8, #3704]
432+
; CHECK-NEXT: mov w8, #56952 // =0xde78
433+
; CHECK-NEXT: movk w8, #15, lsl #16
434+
; CHECK-NEXT: ldrsb w8, [x0, x8]
421435
; CHECK-NEXT: scvtf d0, w8
422436
; CHECK-NEXT: ret
423437
%arrayidx = getelementptr inbounds i8, ptr %a, i64 1039992
@@ -430,8 +444,9 @@ define double @LdOffset_i8_f64(ptr %a) {
430444
define double @LdOffset_i16_f64(ptr %a) {
431445
; CHECK-LABEL: LdOffset_i16_f64:
432446
; CHECK: // %bb.0:
433-
; CHECK-NEXT: add x8, x0, #506, lsl #12 // =2072576
434-
; CHECK-NEXT: ldrsh w8, [x8, #7408]
447+
; CHECK-NEXT: mov w8, #48368 // =0xbcf0
448+
; CHECK-NEXT: movk w8, #31, lsl #16
449+
; CHECK-NEXT: ldrsh w8, [x0, x8]
435450
; CHECK-NEXT: scvtf d0, w8
436451
; CHECK-NEXT: ret
437452
%arrayidx = getelementptr inbounds i16, ptr %a, i64 1039992
@@ -444,8 +459,9 @@ define double @LdOffset_i16_f64(ptr %a) {
444459
define double @LdOffset_i32_f64(ptr %a) {
445460
; CHECK-LABEL: LdOffset_i32_f64:
446461
; CHECK: // %bb.0:
447-
; CHECK-NEXT: add x8, x0, #1012, lsl #12 // =4145152
448-
; CHECK-NEXT: ldr s0, [x8, #14816]
462+
; CHECK-NEXT: mov w8, #31200 // =0x79e0
463+
; CHECK-NEXT: movk w8, #63, lsl #16
464+
; CHECK-NEXT: ldr s0, [x0, x8]
449465
; CHECK-NEXT: ucvtf d0, d0
450466
; CHECK-NEXT: ret
451467
%arrayidx = getelementptr inbounds i32, ptr %a, i64 1039992
@@ -458,8 +474,9 @@ define double @LdOffset_i32_f64(ptr %a) {
458474
define double @LdOffset_i64_f64(ptr %a) {
459475
; CHECK-LABEL: LdOffset_i64_f64:
460476
; CHECK: // %bb.0:
461-
; CHECK-NEXT: add x8, x0, #2024, lsl #12 // =8290304
462-
; CHECK-NEXT: ldr d0, [x8, #29632]
477+
; CHECK-NEXT: mov w8, #62400 // =0xf3c0
478+
; CHECK-NEXT: movk w8, #126, lsl #16
479+
; CHECK-NEXT: ldr d0, [x0, x8]
463480
; CHECK-NEXT: scvtf d0, d0
464481
; CHECK-NEXT: ret
465482
%arrayidx = getelementptr inbounds i64, ptr %a, i64 1039992

0 commit comments

Comments
 (0)