fixup! [RISCV][VLS] Support RISCV VLS calling convention

4vtomat · 4vtomat · commit 0acf8c5824ff · 2024-07-25T02:23:04.000-07:00
diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h
@@ -1942,7 +1942,7 @@ class alignas(TypeAlignment) Type : public ExtQualsTypeCommonBase {
     /// Extra information which affects how the function is called, like
     /// regparm and the calling convention.
     LLVM_PREFERRED_TYPE(CallingConv)
-    unsigned ExtInfo : 17;
+    unsigned ExtInfo : 18;
 
     /// The ref-qualifier associated with a \c FunctionProtoType.
     ///
@@ -4409,7 +4409,7 @@ class FunctionType : public Type {
     };
     enum { NoCfCheckMask = 0x800 };
     enum { CmseNSCallMask = 0x1000 };
-    enum { Log2RISCVABIVLenMask = 0x1E000, Log2RISCVABIVLenOffset = 13 };
+    enum { Log2RISCVABIVLenMask = 0x3E000, Log2RISCVABIVLenOffset = 13 };
     uint32_t Bits = CC_C;
 
     ExtInfo(unsigned Bits) : Bits(static_cast<uint32_t>(Bits)) {}
diff --git a/clang/include/clang/Basic/CodeGenOptions.def b/clang/include/clang/Basic/CodeGenOptions.def
@@ -457,6 +457,9 @@ ENUM_CODEGENOPT(ZeroCallUsedRegs, llvm::ZeroCallUsedRegs::ZeroCallUsedRegsKind,
 /// non-deleting destructors. (No effect on Microsoft ABI.)
 CODEGENOPT(CtorDtorReturnThis, 1, 0)
 
+/// Specify the VLEN for VLS calling convention.
+CODEGENOPT(RISCVABIVLen, 17, 0)
+
 /// FIXME: Make DebugOptions its own top-level .def file.
 #include "DebugOptions.def"
 
diff --git a/clang/include/clang/CodeGen/CGFunctionInfo.h b/clang/include/clang/CodeGen/CGFunctionInfo.h
@@ -609,7 +609,7 @@ class CGFunctionInfo final
   unsigned MaxVectorWidth : 4;
 
   /// Log2 of ABI_VLEN used in RISCV VLS calling convention.
-  unsigned Log2RISCVABIVLen : 4;
+  unsigned Log2RISCVABIVLen : 5;
 
   RequiredArgs Required;
 
diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td
@@ -4866,8 +4866,9 @@ def mrvv_vector_bits_EQ : Joined<["-"], "mrvv-vector-bits=">, Group<m_Group>,
       true: " The value will be reflected in __riscv_v_fixed_vlen preprocessor define"),
     " (RISC-V only)")>;
 def mriscv_abi_vlen_EQ : Joined<["-"], "mriscv-abi-vlen=">, Group<m_Group>,
-                         HelpText<"Specify the VLEN for VLS calling convention.">;
-
+  Visibility<[ClangOption, CC1Option]>,
+  HelpText<"Specify the VLEN for VLS calling convention.">,
+  MarshallingInfoInt<CodeGenOpts<"RISCVABIVLen">>;
 def munaligned_access : Flag<["-"], "munaligned-access">, Group<m_Group>,
   HelpText<"Allow memory accesses to be unaligned (AArch32/MIPSr6 only)">;
 def mno_unaligned_access : Flag<["-"], "mno-unaligned-access">, Group<m_Group>,
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -238,7 +238,8 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {
     else if (ABIStr.ends_with("d"))
       ABIFLen = 64;
     bool EABI = ABIStr.ends_with("e");
-    return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen, EABI);
+    return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen,
+                                        CodeGenOpts.RISCVABIVLen, EABI);
   }
 
   case llvm::Triple::systemz: {
diff --git a/clang/lib/CodeGen/TargetInfo.h b/clang/lib/CodeGen/TargetInfo.h
@@ -519,7 +519,7 @@ createPPC64_SVR4_TargetCodeGenInfo(CodeGenModule &CGM, PPC64_SVR4_ABIKind Kind,
 
 std::unique_ptr<TargetCodeGenInfo>
 createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen, unsigned FLen,
-                             bool EABI);
+                             unsigned ABIVLen, bool EABI);
 
 std::unique_ptr<TargetCodeGenInfo>
 createCommonSPIRTargetCodeGenInfo(CodeGenModule &CGM);
diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -26,6 +26,7 @@ class RISCVABIInfo : public DefaultABIInfo {
   // ISA might have a wider FLen than the selected ABI (e.g. an RV32IF target
   // with soft float ABI has FLen==0).
   unsigned FLen;
+  unsigned ABIVLen;
   const int NumArgGPRs;
   const int NumArgFPRs;
   const bool EABI;
@@ -37,17 +38,17 @@ class RISCVABIInfo : public DefaultABIInfo {
 
 public:
   RISCVABIInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen, unsigned FLen,
-               bool EABI)
-      : DefaultABIInfo(CGT), XLen(XLen), FLen(FLen), NumArgGPRs(EABI ? 6 : 8),
-        NumArgFPRs(FLen != 0 ? 8 : 0), EABI(EABI) {}
+               unsigned ABIVLen, bool EABI)
+      : DefaultABIInfo(CGT), XLen(XLen), FLen(FLen), ABIVLen(ABIVLen),
+        NumArgGPRs(EABI ? 6 : 8), NumArgFPRs(FLen != 0 ? 8 : 0), EABI(EABI) {}
 
   // DefaultABIInfo's classifyReturnType and classifyArgumentType are
   // non-virtual, but computeInfo is virtual, so we overload it.
   void computeInfo(CGFunctionInfo &FI) const override;
 
   ABIArgInfo classifyArgumentType(QualType Ty, bool IsFixed, int &ArgGPRsLeft,
-                                  int &ArgFPRsLeft, unsigned ABIVLen) const;
-  ABIArgInfo classifyReturnType(QualType RetTy, unsigned ABIVLen) const;
+                                  int &ArgFPRsLeft, unsigned ArgABIVLen) const;
+  ABIArgInfo classifyReturnType(QualType RetTy, unsigned ArgABIVLen) const;
 
   RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
                    AggValueSlot Slot) const override;
@@ -63,23 +64,18 @@ class RISCVABIInfo : public DefaultABIInfo {
                                                llvm::Type *Field2Ty,
                                                CharUnits Field2Off) const;
 
-  ABIArgInfo coerceVLSVector(QualType Ty, unsigned ABIVLen = 0) const;
+  ABIArgInfo coerceVLSVector(QualType Ty, unsigned ArgABIVLen = 0) const;
 };
 } // end anonymous namespace
 
 void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
-  unsigned ABIVLen = 1 << FI.getExtInfo().getLog2RISCVABIVLen();
-  if (ABIVLen == 1)
-    // No riscv_vls_cc in the function, check if there's one passed from
-    // compiler options.
-    for (unsigned i = 5; i <= 16; ++i)
-      if (getContext().getTargetInfo().getTargetOpts().FeatureMap.contains(
-              "abi-vlen-" + llvm::utostr(1 << i) + "b"))
-        ABIVLen = 1 << i;
+  unsigned ArgABIVLen = 1 << FI.getExtInfo().getLog2RISCVABIVLen();
+  if (ArgABIVLen == 1)
+    ArgABIVLen = ABIVLen;
 
   QualType RetTy = FI.getReturnType();
   if (!getCXXABI().classifyReturnType(FI))
-    FI.getReturnInfo() = classifyReturnType(RetTy, ABIVLen);
+    FI.getReturnInfo() = classifyReturnType(RetTy, ArgABIVLen);
 
   // IsRetIndirect is true if classifyArgumentType indicated the value should
   // be passed indirect, or if the type size is a scalar greater than 2*XLen
@@ -106,7 +102,7 @@ void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
   for (auto &ArgInfo : FI.arguments()) {
     bool IsFixed = ArgNum < NumFixedArgs;
     ArgInfo.info = classifyArgumentType(ArgInfo.type, IsFixed, ArgGPRsLeft,
-                                        ArgFPRsLeft, ABIVLen);
+                                        ArgFPRsLeft, ArgABIVLen);
     ArgNum++;
   }
 }
@@ -327,7 +323,8 @@ ABIArgInfo RISCVABIInfo::coerceAndExpandFPCCEligibleStruct(
 
 // Fixed-length RVV vectors are represented as scalable vectors in function
 // args/return and must be coerced from fixed vectors.
-ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty, unsigned ABIVLen) const {
+ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty,
+                                         unsigned ArgABIVLen) const {
   assert(Ty->isVectorType() && "expected vector type!");
 
   const auto *VT = Ty->castAs<VectorType>();
@@ -337,7 +334,7 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty, unsigned ABIVLen) const {
   llvm::ScalableVectorType *ResType;
   llvm::Type *EltType = CGT.ConvertType(VT->getElementType());
 
-  if (ABIVLen == 0) {
+  if (ArgABIVLen == 0) {
     // RVV fixed-length vector
     auto VScale =
         getContext().getTargetInfo().getVScaleRange(getContext().getLangOpts());
@@ -355,7 +352,7 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty, unsigned ABIVLen) const {
   } else {
     // Generic vector
     ResType = llvm::ScalableVectorType::get(
-        EltType, NumElts * llvm::RISCV::RVVBitsPerBlock / ABIVLen);
+        EltType, NumElts * llvm::RISCV::RVVBitsPerBlock / ArgABIVLen);
   }
 
   return ABIArgInfo::getDirect(ResType);
@@ -364,7 +361,7 @@ ABIArgInfo RISCVABIInfo::coerceVLSVector(QualType Ty, unsigned ABIVLen) const {
 ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
                                               int &ArgGPRsLeft,
                                               int &ArgFPRsLeft,
-                                              unsigned ABIVLen) const {
+                                              unsigned ArgABIVLen) const {
   assert(ArgGPRsLeft <= NumArgGPRs && "Arg GPR tracking underflow");
   Ty = useFirstFieldIfTransparentUnion(Ty);
 
@@ -471,10 +468,10 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
     if (VT->getVectorKind() == VectorKind::RVVFixedLengthData ||
         VT->getVectorKind() == VectorKind::RVVFixedLengthMask)
       return coerceVLSVector(Ty);
-    if (VT->getVectorKind() == VectorKind::Generic && ABIVLen != 1)
+    if (VT->getVectorKind() == VectorKind::Generic && ArgABIVLen != 0)
       // Generic vector without riscv_vls_cc should fall through and pass by
       // reference.
-      return coerceVLSVector(Ty, ABIVLen);
+      return coerceVLSVector(Ty, ArgABIVLen);
   }
 
   // Aggregates which are <= 2*XLen will be passed in registers if possible,
@@ -499,7 +496,7 @@ ABIArgInfo RISCVABIInfo::classifyArgumentType(QualType Ty, bool IsFixed,
 }
 
 ABIArgInfo RISCVABIInfo::classifyReturnType(QualType RetTy,
-                                            unsigned ABIVLen) const {
+                                            unsigned ArgABIVLen) const {
   if (RetTy->isVoidType())
     return ABIArgInfo::getIgnore();
 
@@ -509,7 +506,7 @@ ABIArgInfo RISCVABIInfo::classifyReturnType(QualType RetTy,
   // The rules for return and argument types are the same, so defer to
   // classifyArgumentType.
   return classifyArgumentType(RetTy, /*IsFixed=*/true, ArgGPRsLeft, ArgFPRsLeft,
-                              ABIVLen);
+                              ArgABIVLen);
 }
 
 RValue RISCVABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
@@ -548,9 +545,9 @@ namespace {
 class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
 public:
   RISCVTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, unsigned XLen,
-                         unsigned FLen, bool EABI)
+                         unsigned FLen, unsigned ABIVLen, bool EABI)
       : TargetCodeGenInfo(
-            std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, EABI)) {
+            std::make_unique<RISCVABIInfo>(CGT, XLen, FLen, ABIVLen, EABI)) {
     SwiftInfo =
         std::make_unique<SwiftABIInfo>(CGT, /*SwiftErrorInRegister=*/false);
   }
@@ -579,7 +576,8 @@ class RISCVTargetCodeGenInfo : public TargetCodeGenInfo {
 
 std::unique_ptr<TargetCodeGenInfo>
 CodeGen::createRISCVTargetCodeGenInfo(CodeGenModule &CGM, unsigned XLen,
-                                      unsigned FLen, bool EABI) {
+                                      unsigned FLen, unsigned ABIVLen,
+                                      bool EABI) {
   return std::make_unique<RISCVTargetCodeGenInfo>(CGM.getTypes(), XLen, FLen,
-                                                  EABI);
+                                                  ABIVLen, EABI);
 }
diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -95,10 +95,6 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
       CPUFastVectorUnaligned = true;
   }
 
-  if (Arg *A = Args.getLastArg(options::OPT_mriscv_abi_vlen_EQ))
-    Features.push_back(
-        Args.MakeArgString(Twine("+abi-vlen-") + A->getValue() + "b"));
-
   // Handle features corresponding to "-ffixed-X" options
   if (Args.hasArg(options::OPT_ffixed_x1))
     Features.push_back("+reserve-x1");
diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp
@@ -2206,6 +2206,10 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
           << A->getSpelling() << Val;
     }
   }
+
+  if (Arg *A = Args.getLastArg(options::OPT_mriscv_abi_vlen_EQ))
+    CmdArgs.push_back(
+        Args.MakeArgString(Twine("-mriscv-abi-vlen=") + A->getValue()));
 }
 
 void Clang::AddSparcTargetArgs(const ArgList &Args,
diff --git a/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c b/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.c
@@ -3,9 +3,9 @@
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
 // RUN: %clang_cc1 -std=c23 -triple riscv64 -target-feature +v \
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
-// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +abi-vlen-256b \
+// RUN: %clang_cc1 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +v \
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN %s
-// RUN: %clang_cc1 -std=c23 -triple riscv64 -target-feature +v -target-feature +abi-vlen-256b \
+// RUN: %clang_cc1 -std=c23 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +v \
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN %s
 
 #include <riscv_vector.h>
diff --git a/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp b/clang/test/CodeGen/RISCV/riscv-vector-callingconv-llvm-ir.cpp
@@ -1,7 +1,7 @@
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +v \
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM %s
-// RUN: %clang_cc1 -std=c++11 -triple riscv64 -target-feature +v -target-feature +abi-vlen-256b \
+// RUN: %clang_cc1 -std=c++11 -triple riscv64 -mriscv-abi-vlen=256 -target-feature +v \
 // RUN:   -emit-llvm %s -o - | FileCheck -check-prefix=CHECK-LLVM-ABI-VLEN %s
 
 #include <riscv_vector.h>
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1333,15 +1333,6 @@ def Experimental
    : SubtargetFeature<"experimental", "HasExperimental",
                       "true", "Experimental intrinsics">;
 
-def FeatureABIVLen32B
-  : SubtargetFeature<"abi-vlen-32b", "ABIVLen", "32", "ABI_VLEN desc">;
-
-foreach i = { 6-16 } in {
-  defvar I = !shl(1, i);
-  def FeatureABIVLen # I # B
-    : SubtargetFeature<"abi-vlen-"#I#"b", "ABIVLen", !cast<string>(I), "ABI_VLEN desc">;
-}
-
 // Some vector hardware implementations do not process all VLEN bits in parallel
 // and instead split over multiple cycles. DLEN refers to the datapath width
 // that can be done in parallel.
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -75,7 +75,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
 #include "RISCVGenSubtargetInfo.inc"
 
   unsigned ZvlLen = 0;
-  unsigned ABIVLen = 0;
   unsigned RVVVectorBitsMin;
   unsigned RVVVectorBitsMax;
   uint8_t MaxInterleaveFactor = 2;

Original file line number	Diff line number	Diff line change
`@@ -238,7 +238,8 @@ createTargetCodeGenInfo(CodeGenModule &CGM) {`
`238`	`238`	`else if (ABIStr.ends_with("d"))`
`239`	`239`	`ABIFLen = 64;`
`240`	`240`	`bool EABI = ABIStr.ends_with("e");`
`241`		`- return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen, EABI);`
	`241`	`+ return createRISCVTargetCodeGenInfo(CGM, XLen, ABIFLen,`
	`242`	`+ CodeGenOpts.RISCVABIVLen, EABI);`
`242`	`243`	`}`
`243`	`244`
`244`	`245`	`case llvm::Triple::systemz: {`
Original file line number	Diff line number	Diff line change
`@@ -2206,6 +2206,10 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,`
`2206`	`2206`	`<< A->getSpelling() << Val;`
`2207`	`2207`	`}`
`2208`	`2208`	`}`
	`2209`	`+`
	`2210`	`+ if (Arg *A = Args.getLastArg(options::OPT_mriscv_abi_vlen_EQ))`
	`2211`	`+ CmdArgs.push_back(`
	`2212`	`+ Args.MakeArgString(Twine("-mriscv-abi-vlen=") + A->getValue()));`
`2209`	`2213`	`}`
`2210`	`2214`
`2211`	`2215`	`void Clang::AddSparcTargetArgs(const ArgList &Args,`