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[DAG] visitSUB - update the ABS matching code to use SDPatternMatch and hasOperation.
Avoids the need to explicitly test both commuted variants and doesn't match custom lowering after legalization. Cleanup for #94504
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llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4041,17 +4041,11 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
40414041
return DAG.getNode(ISD::ADD, DL, VT, N0, SExt);
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}
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4044-
// fold Y = sra (X, size(X)-1); sub (xor (X, Y), Y) -> (abs X)
4045-
if (TLI.isOperationLegalOrCustom(ISD::ABS, VT)) {
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if (N0.getOpcode() == ISD::XOR && N1.getOpcode() == ISD::SRA) {
4047-
SDValue X0 = N0.getOperand(0), X1 = N0.getOperand(1);
4048-
SDValue S0 = N1.getOperand(0);
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if ((X0 == S0 && X1 == N1) || (X0 == N1 && X1 == S0))
4050-
if (ConstantSDNode *C = isConstOrConstSplat(N1.getOperand(1)))
4051-
if (C->getAPIntValue() == (BitWidth - 1))
4052-
return DAG.getNode(ISD::ABS, DL, VT, S0);
4053-
}
4054-
}
4044+
// fold B = sra (A, size(A)-1); sub (xor (A, B), B) -> (abs A)
4045+
if (hasOperation(ISD::ABS, VT) &&
4046+
sd_match(N1, m_Sra(m_Value(A), m_SpecificInt(BitWidth - 1))) &&
4047+
sd_match(N0, m_Xor(m_Specific(A), m_Specific(N1))))
4048+
return DAG.getNode(ISD::ABS, DL, VT, A);
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// If the relocation model supports it, consider symbol offsets.
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if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0))

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