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Merge pull request #116 from farcaller/fix-lifetimes
Fixing a bunch of nightly fallouts Reviewed-by: bgamari
2 parents 04e81fb + db6ff40 commit 4c04075

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-4
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6 files changed

+8
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.travis.yml

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@@ -8,6 +8,8 @@ install:
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- tar xf rust.tgz
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- (cd ./rust-nightly-x86_64-unknown-linux-gnu/; sudo ./install.sh)
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- export LD_LIBRARY_PATH=/usr/local/lib
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- (mkdir -p ./thirdparty; cd ./thirdparty; git clone --depth 50 https://github.com/rust-lang/rust)
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- "(cd ./thirdparty/rust; git checkout `rustc --version|awk '{sub(/\\(/, \"\", $3); print $3}'`)"
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before_script:
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- rustc --version
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script:

Rakefile

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@@ -75,6 +75,7 @@ compile_rust :platformtree_crate, {
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produce: 'platformtree/platformtree.rs'.in_root.as_rlib.in_build,
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out_dir: true,
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build_for: :host,
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optimize: 0,
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}
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rust_tests :platformtree_test, {
@@ -98,6 +99,7 @@ compile_rust :macro_platformtree, {
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produce: 'macro/platformtree.rs'.in_root.as_dylib.in_build,
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out_dir: true,
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build_for: :host,
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optimize: 0,
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}
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desc "Build API documentation"

src/hal/k20/uart.rs

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@@ -78,7 +78,7 @@ enum ParitySelect {
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}
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impl UARTPeripheral {
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fn reg(self) -> &reg::UART {
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fn reg(self) -> &'static reg::UART {
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match self {
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UART0 => &reg::UART0,
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UART1 => &reg::UART1,

src/hal/lpc17xx/peripheral_clock.rs

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@@ -195,7 +195,7 @@ impl PeripheralClock {
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}
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}
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fn divisor_reg_and_offset(self) -> (&reg::PCLKSEL, u32) {
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fn divisor_reg_and_offset(self) -> (&'static reg::PCLKSEL, u32) {
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match self.to_divisor() {
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WDTDivisor|TIMER0Divisor|TIMER1Divisor|UART0Divisor|UART1Divisor|
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PWM1Divisor|I2C0Divisor|SPIDivisor|SSP1Divisor|DACDivisor|ADCDivisor|

src/hal/lpc17xx/uart.rs

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@@ -113,7 +113,7 @@ pub struct UART {
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}
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impl UARTPeripheral {
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fn reg(self) -> &reg::UART {
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fn reg(self) -> &'static reg::UART {
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match self {
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UART0 => &reg::UART0,
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UART2 => &reg::UART2,

support/build/rlib.rb

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@@ -17,6 +17,6 @@
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module Rlib
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def self.crate_name(src)
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`#{RUSTC} --print-file-name "#{src}"`
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`#{RUSTC} --print-file-name "#{src}"`.strip
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end
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end

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