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Sebastian Pop
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[AArch64] add barriers to ool __sync builtins
2022-05-13 Sebastian Pop <[email protected]> gcc/ PR target/105162 * config/aarch64/aarch64-protos.h (atomic_ool_names): Increase dimension of str array. * config/aarch64/aarch64.cc (aarch64_atomic_ool_func): Call memmodel_from_int and handle MEMMODEL_SYNC_*. (DEF0): Add __aarch64_*_sync functions. gcc/testsuite/ PR target/105162 * gcc.target/aarch64/sync-comp-swap-ool.c: New. * gcc.target/aarch64/sync-op-acquire-ool.c: New. * gcc.target/aarch64/sync-op-full-ool.c: New. * gcc.target/aarch64/target_attr_20.c: Update check. * gcc.target/aarch64/target_attr_21.c: Same. libgcc/ PR target/105162 * config/aarch64/lse.S: Define BARRIER and handle memory MODEL 5. * config/aarch64/t-lse: Add a 5th memory model for _sync functions.
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-14
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+75
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‎gcc/config/aarch64/aarch64-protos.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1065,7 +1065,7 @@ bool aarch64_high_bits_all_ones_p (HOST_WIDE_INT);
10651065

10661066
struct atomic_ool_names
10671067
{
1068-
const char *str[5][4];
1068+
const char *str[5][5];
10691069
};
10701070

10711071
rtx aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,

‎gcc/config/aarch64/aarch64.cc

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -22678,14 +22678,14 @@ aarch64_emit_unlikely_jump (rtx insn)
2267822678
add_reg_br_prob_note (jump, profile_probability::very_unlikely ());
2267922679
}
2268022680

22681-
/* We store the names of the various atomic helpers in a 5x4 array.
22681+
/* We store the names of the various atomic helpers in a 5x5 array.
2268222682
Return the libcall function given MODE, MODEL and NAMES. */
2268322683

2268422684
rtx
2268522685
aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,
2268622686
const atomic_ool_names *names)
2268722687
{
22688-
memmodel model = memmodel_base (INTVAL (model_rtx));
22688+
memmodel model = memmodel_from_int (INTVAL (model_rtx));
2268922689
int mode_idx, model_idx;
2269022690

2269122691
switch (mode)
@@ -22725,6 +22725,11 @@ aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,
2272522725
case MEMMODEL_SEQ_CST:
2272622726
model_idx = 3;
2272722727
break;
22728+
case MEMMODEL_SYNC_ACQUIRE:
22729+
case MEMMODEL_SYNC_RELEASE:
22730+
case MEMMODEL_SYNC_SEQ_CST:
22731+
model_idx = 4;
22732+
break;
2272822733
default:
2272922734
gcc_unreachable ();
2273022735
}
@@ -22737,7 +22742,8 @@ aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx,
2273722742
{ "__aarch64_" #B #N "_relax", \
2273822743
"__aarch64_" #B #N "_acq", \
2273922744
"__aarch64_" #B #N "_rel", \
22740-
"__aarch64_" #B #N "_acq_rel" }
22745+
"__aarch64_" #B #N "_acq_rel", \
22746+
"__aarch64_" #B #N "_sync" }
2274122747

2274222748
#define DEF4(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), \
2274322749
{ NULL, NULL, NULL, NULL }

‎gcc/testsuite/gcc.target/aarch64/sync-comp-swap-ool.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
/* { dg-do compile } */
2+
/* { dg-options "-march=armv8-a+nolse -O2 -fno-ipa-icf -moutline-atomics" } */
3+
4+
#include "sync-comp-swap.x"
5+
6+
/* { dg-final { scan-assembler-times "bl.*__aarch64_cas4_sync" 1 } } */

‎gcc/testsuite/gcc.target/aarch64/sync-op-acquire-ool.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,6 @@
1+
/* { dg-do compile } */
2+
/* { dg-options "-march=armv8-a+nolse -O2 -moutline-atomics" } */
3+
4+
#include "sync-op-acquire.x"
5+
6+
/* { dg-final { scan-assembler-times "bl.*__aarch64_swp4_sync" 1 } } */

‎gcc/testsuite/gcc.target/aarch64/sync-op-full-ool.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,9 @@
1+
/* { dg-do compile } */
2+
/* { dg-options "-march=armv8-a+nolse -O2 -moutline-atomics" } */
3+
4+
#include "sync-op-full.x"
5+
6+
/* { dg-final { scan-assembler-times "bl.*__aarch64_ldadd4_sync" 1 } } */
7+
/* { dg-final { scan-assembler-times "bl.*__aarch64_ldclr4_sync" 1 } } */
8+
/* { dg-final { scan-assembler-times "bl.*__aarch64_ldeor4_sync" 1 } } */
9+
/* { dg-final { scan-assembler-times "bl.*__aarch64_ldset4_sync" 1 } } */

‎gcc/testsuite/gcc.target/aarch64/target_attr_20.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,4 +24,4 @@ bar (void)
2424
}
2525
}
2626

27-
/* { dg-final { scan-assembler-not "bl.*__aarch64_cas2_acq_rel" } } */
27+
/* { dg-final { scan-assembler-not "bl.*__aarch64_cas2_sync" } } */

‎gcc/testsuite/gcc.target/aarch64/target_attr_21.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -24,4 +24,4 @@ bar (void)
2424
}
2525
}
2626

27-
/* { dg-final { scan-assembler-times "bl.*__aarch64_cas2_acq_rel" 1 } } */
27+
/* { dg-final { scan-assembler-times "bl.*__aarch64_cas2_sync" 1 } } */

‎libgcc/config/aarch64/lse.S

Lines changed: 38 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -87,24 +87,44 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
8787
# define L
8888
# define M 0x000000
8989
# define N 0x000000
90+
# define BARRIER
9091
#elif MODEL == 2
9192
# define SUFF _acq
9293
# define A a
9394
# define L
9495
# define M 0x400000
9596
# define N 0x800000
97+
# define BARRIER
9698
#elif MODEL == 3
9799
# define SUFF _rel
98100
# define A
99101
# define L l
100102
# define M 0x008000
101103
# define N 0x400000
104+
# define BARRIER
102105
#elif MODEL == 4
103106
# define SUFF _acq_rel
104107
# define A a
105108
# define L l
106109
# define M 0x408000
107110
# define N 0xc00000
111+
# define BARRIER
112+
#elif MODEL == 5
113+
# define SUFF _sync
114+
#ifdef L_swp
115+
/* swp has _acq semantics. */
116+
# define A a
117+
# define L
118+
# define M 0x400000
119+
# define N 0x800000
120+
#else
121+
/* All other _sync functions have _seq semantics. */
122+
# define A a
123+
# define L l
124+
# define M 0x408000
125+
# define N 0xc00000
126+
#endif
127+
# define BARRIER dmb ish
108128
#else
109129
# error
110130
#endif
@@ -127,7 +147,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
127147
#endif
128148

129149
#define NAME(BASE) glue4(__aarch64_, BASE, SIZE, SUFF)
130-
#define LDXR glue4(ld, A, xr, S)
150+
#if MODEL == 5
151+
/* Drop A for _sync functions. */
152+
# define LDXR glue3(ld, xr, S)
153+
#else
154+
# define LDXR glue4(ld, A, xr, S)
155+
#endif
131156
#define STXR glue4(st, L, xr, S)
132157

133158
/* Temporary registers used. Other than these, only the return value
@@ -183,10 +208,16 @@ STARTFN NAME(cas)
183208
bne 1f
184209
STXR w(tmp1), s(1), [x2]
185210
cbnz w(tmp1), 0b
186-
1: ret
211+
1: BARRIER
212+
ret
187213

188214
#else
189-
#define LDXP glue3(ld, A, xp)
215+
#if MODEL == 5
216+
/* Drop A for _sync functions. */
217+
# define LDXP glue2(ld, xp)
218+
#else
219+
# define LDXP glue3(ld, A, xp)
220+
#endif
190221
#define STXP glue3(st, L, xp)
191222
#ifdef HAVE_AS_LSE
192223
# define CASP glue3(casp, A, L) x0, x1, x2, x3, [x4]
@@ -205,7 +236,8 @@ STARTFN NAME(cas)
205236
bne 1f
206237
STXP w(tmp2), x2, x3, [x4]
207238
cbnz w(tmp2), 0b
208-
1: ret
239+
1: BARRIER
240+
ret
209241

210242
#endif
211243

@@ -229,6 +261,7 @@ STARTFN NAME(swp)
229261
0: LDXR s(0), [x1]
230262
STXR w(tmp1), s(tmp0), [x1]
231263
cbnz w(tmp1), 0b
264+
BARRIER
232265
ret
233266

234267
ENDFN NAME(swp)
@@ -273,6 +306,7 @@ STARTFN NAME(LDNM)
273306
OP s(tmp1), s(0), s(tmp0)
274307
STXR w(tmp2), s(tmp1), [x1]
275308
cbnz w(tmp2), 0b
309+
BARRIER
276310
ret
277311

278312
ENDFN NAME(LDNM)

‎libgcc/config/aarch64/t-lse

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,13 +18,13 @@
1818
# along with GCC; see the file COPYING3. If not see
1919
# <http://www.gnu.org/licenses/>.
2020

21-
# Compare-and-swap has 5 sizes and 4 memory models.
21+
# Compare-and-swap has 5 sizes and 5 memory models.
2222
S0 := $(foreach s, 1 2 4 8 16, $(addsuffix _$(s), cas))
23-
O0 := $(foreach m, 1 2 3 4, $(addsuffix _$(m)$(objext), $(S0)))
23+
O0 := $(foreach m, 1 2 3 4 5, $(addsuffix _$(m)$(objext), $(S0)))
2424

25-
# Swap, Load-and-operate have 4 sizes and 4 memory models
25+
# Swap, Load-and-operate have 4 sizes and 5 memory models
2626
S1 := $(foreach s, 1 2 4 8, $(addsuffix _$(s), swp ldadd ldclr ldeor ldset))
27-
O1 := $(foreach m, 1 2 3 4, $(addsuffix _$(m)$(objext), $(S1)))
27+
O1 := $(foreach m, 1 2 3 4 5, $(addsuffix _$(m)$(objext), $(S1)))
2828

2929
LSE_OBJS := $(O0) $(O1)
3030

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