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libraries/SPISlave/src/hspi_slave.c

+19-25
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,9 @@
11
/*
2+
Changes:
3+
30.10.2018: Ack: Timing for MISO corrected, some comments added.
4+
hspi_slave_setStatus in RAM
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13.01.2019: Ack: Comments added
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27
SPISlave library for esp8266
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49
Copyright (c) 2015 Hristo Gochkov. All rights reserved.
@@ -85,36 +90,25 @@ void hspi_slave_begin(uint8_t status_len, void * arg)
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pinMode(MISO, SPECIAL);
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pinMode(MOSI, SPECIAL);
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88-
SPI1S = SPISE | SPISBE | 0x3E0;
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SPI1U = SPIUMISOH | SPIUCOMMAND | SPIUSSE;
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SPI1S = SPISE | SPISBE | 0x3E0; // SPI_SLAVE_REG
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SPI1U = SPIUMISOH | SPIUCOMMAND | SPIUSSE; //SPI_USER_REG
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SPI1CLK = 0;
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SPI1U2 = (7 << SPILCOMMAND);
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SPI1S1 = (((status_len * 8) - 1) << SPIS1LSTA) | (0xff << SPIS1LBUF) | (7 << SPIS1LWBA) | (7 << SPIS1LRBA) | SPIS1RSTA;
93-
SPI1P = (1 << 19);
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SPI1CMD = SPIBUSY;
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SPI1C2=(0x2<<SPIC2MOSIDN_S) | (0x1<<SPIC2MISODM_S); // GuaAck. 30.10.2018; timing of MISO
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SPI1U2 = (7 << SPILCOMMAND); // SPI_USER2_REG
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SPI1S1 = (((status_len * 8) - 1) << SPIS1LSTA) | (0xff << SPIS1LBUF) | (7 << SPIS1LWBA) | (7 << SPIS1LRBA) | SPIS1RSTA; //SPI_SLAVE1_REG
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SPI1P = (1 << 19); // not described in ESP32-reference
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SPI1CMD = SPIBUSY; // not described in ESP32-reference
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// (no settings in SPI1C2 in the original version.)
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SPI1C2=(0x2<<SPIC2MOSIDN_S) | (0x1<<SPIC2MISODM_S); // Ack. 30.10.2018; timing of MISO//
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// SPIC2MISODM_S (SPI_MISO_DELAY_MODE) = 1, makes slave to change MISO value on falling edge on CLK signal
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// es it should for SPI-Mode = 1
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// SPIC2MOSIDN_S (SPI_MOSI_DELAY_NUM) = 2: Probably not required, but all tests are done with this setting
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ETS_SPI_INTR_ATTACH(_hspi_slave_isr_handler,arg);
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ETS_SPI_INTR_ENABLE();
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}
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void ICACHE_RAM_ATTR hspi_slave_setStatus(uint32_t status)
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// put in RAM as setStatus is often called from an interrupt routine
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100-
void hspi_slave_end()
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{
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ETS_SPI_INTR_DISABLE();
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ETS_SPI_INTR_ATTACH(NULL, NULL);
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pinMode(SS, INPUT);
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pinMode(SCK, INPUT);
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pinMode(MISO, INPUT);
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pinMode(MOSI, INPUT);
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// defaults
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SPI1S = 0;
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SPI1U = SPIUSSE | SPIUCOMMAND;
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SPI1S1 = 0;
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SPI1P = B110;
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}
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void ICACHE_RAM_ATTR hspi_slave_setStatus(uint32_t status) // GuaAck. 30.10.2018
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{
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SPI1WS = status;
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}

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