|
1 | 1 | /*
|
| 2 | +Changes: |
| 3 | +30.10.2018: Ack: Timing for MISO corrected, some comments added. |
| 4 | + hspi_slave_setStatus in RAM |
| 5 | +13.01.2019: Ack: Comments added |
| 6 | +
|
2 | 7 | SPISlave library for esp8266
|
3 | 8 |
|
4 | 9 | Copyright (c) 2015 Hristo Gochkov. All rights reserved.
|
@@ -85,36 +90,25 @@ void hspi_slave_begin(uint8_t status_len, void * arg)
|
85 | 90 | pinMode(MISO, SPECIAL);
|
86 | 91 | pinMode(MOSI, SPECIAL);
|
87 | 92 |
|
88 |
| - SPI1S = SPISE | SPISBE | 0x3E0; |
89 |
| - SPI1U = SPIUMISOH | SPIUCOMMAND | SPIUSSE; |
| 93 | + SPI1S = SPISE | SPISBE | 0x3E0; // SPI_SLAVE_REG |
| 94 | + SPI1U = SPIUMISOH | SPIUCOMMAND | SPIUSSE; //SPI_USER_REG |
90 | 95 | SPI1CLK = 0;
|
91 |
| - SPI1U2 = (7 << SPILCOMMAND); |
92 |
| - SPI1S1 = (((status_len * 8) - 1) << SPIS1LSTA) | (0xff << SPIS1LBUF) | (7 << SPIS1LWBA) | (7 << SPIS1LRBA) | SPIS1RSTA; |
93 |
| - SPI1P = (1 << 19); |
94 |
| - SPI1CMD = SPIBUSY; |
95 |
| - SPI1C2=(0x2<<SPIC2MOSIDN_S) | (0x1<<SPIC2MISODM_S); // GuaAck. 30.10.2018; timing of MISO |
| 96 | + SPI1U2 = (7 << SPILCOMMAND); // SPI_USER2_REG |
| 97 | + SPI1S1 = (((status_len * 8) - 1) << SPIS1LSTA) | (0xff << SPIS1LBUF) | (7 << SPIS1LWBA) | (7 << SPIS1LRBA) | SPIS1RSTA; //SPI_SLAVE1_REG |
| 98 | + SPI1P = (1 << 19); // not described in ESP32-reference |
| 99 | + SPI1CMD = SPIBUSY; // not described in ESP32-reference |
| 100 | +// (no settings in SPI1C2 in the original version.) |
| 101 | + SPI1C2=(0x2<<SPIC2MOSIDN_S) | (0x1<<SPIC2MISODM_S); // Ack. 30.10.2018; timing of MISO// |
| 102 | +// SPIC2MISODM_S (SPI_MISO_DELAY_MODE) = 1, makes slave to change MISO value on falling edge on CLK signal |
| 103 | +// es it should for SPI-Mode = 1 |
| 104 | +// SPIC2MOSIDN_S (SPI_MOSI_DELAY_NUM) = 2: Probably not required, but all tests are done with this setting |
96 | 105 | ETS_SPI_INTR_ATTACH(_hspi_slave_isr_handler,arg);
|
97 | 106 | ETS_SPI_INTR_ENABLE();
|
98 | 107 | }
|
| 108 | + |
| 109 | +void ICACHE_RAM_ATTR hspi_slave_setStatus(uint32_t status) |
| 110 | +// put in RAM as setStatus is often called from an interrupt routine |
99 | 111 |
|
100 |
| -void hspi_slave_end() |
101 |
| -{ |
102 |
| - ETS_SPI_INTR_DISABLE(); |
103 |
| - ETS_SPI_INTR_ATTACH(NULL, NULL); |
104 |
| - |
105 |
| - pinMode(SS, INPUT); |
106 |
| - pinMode(SCK, INPUT); |
107 |
| - pinMode(MISO, INPUT); |
108 |
| - pinMode(MOSI, INPUT); |
109 |
| - |
110 |
| - // defaults |
111 |
| - SPI1S = 0; |
112 |
| - SPI1U = SPIUSSE | SPIUCOMMAND; |
113 |
| - SPI1S1 = 0; |
114 |
| - SPI1P = B110; |
115 |
| -} |
116 |
| - |
117 |
| -void ICACHE_RAM_ATTR hspi_slave_setStatus(uint32_t status) // GuaAck. 30.10.2018 |
118 | 112 | {
|
119 | 113 | SPI1WS = status;
|
120 | 114 | }
|
|
0 commit comments