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104 | 104 | S3C2410_UCON_RXIRQMODE | \
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105 | 105 | S3C2410_UCON_RXFIFO_TOI)
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106 | 106 |
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| 107 | +#define S3C64XX_UCON_TXBURST_1 (0<<20) |
| 108 | +#define S3C64XX_UCON_TXBURST_4 (1<<20) |
| 109 | +#define S3C64XX_UCON_TXBURST_8 (2<<20) |
| 110 | +#define S3C64XX_UCON_TXBURST_16 (3<<20) |
| 111 | +#define S3C64XX_UCON_TXBURST_MASK (0xf<<20) |
| 112 | +#define S3C64XX_UCON_RXBURST_1 (0<<16) |
| 113 | +#define S3C64XX_UCON_RXBURST_4 (1<<16) |
| 114 | +#define S3C64XX_UCON_RXBURST_8 (2<<16) |
| 115 | +#define S3C64XX_UCON_RXBURST_16 (3<<16) |
| 116 | +#define S3C64XX_UCON_RXBURST_MASK (0xf<<16) |
| 117 | +#define S3C64XX_UCON_TIMEOUT_SHIFT (12) |
| 118 | +#define S3C64XX_UCON_TIMEOUT_MASK (0xf<<12) |
| 119 | +#define S3C64XX_UCON_EMPTYINT_EN (1<<11) |
| 120 | +#define S3C64XX_UCON_DMASUS_EN (1<<10) |
| 121 | +#define S3C64XX_UCON_TXINT_LEVEL (1<<9) |
| 122 | +#define S3C64XX_UCON_RXINT_LEVEL (1<<8) |
| 123 | +#define S3C64XX_UCON_TIMEOUT_EN (1<<7) |
| 124 | +#define S3C64XX_UCON_ERRINT_EN (1<<6) |
| 125 | +#define S3C64XX_UCON_TXMODE_DMA (2<<2) |
| 126 | +#define S3C64XX_UCON_TXMODE_CPU (1<<2) |
| 127 | +#define S3C64XX_UCON_TXMODE_MASK (3<<2) |
| 128 | +#define S3C64XX_UCON_RXMODE_DMA (2<<0) |
| 129 | +#define S3C64XX_UCON_RXMODE_CPU (1<<0) |
| 130 | +#define S3C64XX_UCON_RXMODE_MASK (3<<0) |
| 131 | + |
107 | 132 | #define S3C2410_UFCON_FIFOMODE (1<<0)
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108 | 133 | #define S3C2410_UFCON_TXTRIG0 (0<<6)
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109 | 134 | #define S3C2410_UFCON_RXTRIG8 (1<<4)
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155 | 180 | #define S3C2440_UFSTAT_TXMASK (63<<8)
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156 | 181 | #define S3C2440_UFSTAT_RXMASK (63)
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157 | 182 |
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| 183 | +#define S3C2410_UTRSTAT_TIMEOUT (1<<3) |
158 | 184 | #define S3C2410_UTRSTAT_TXE (1<<2)
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159 | 185 | #define S3C2410_UTRSTAT_TXFE (1<<1)
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160 | 186 | #define S3C2410_UTRSTAT_RXDR (1<<0)
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179 | 205 | #define S3C64XX_UINTM 0x38
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180 | 206 |
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181 | 207 | #define S3C64XX_UINTM_RXD (0)
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| 208 | +#define S3C64XX_UINTM_ERROR (1) |
182 | 209 | #define S3C64XX_UINTM_TXD (2)
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183 | 210 | #define S3C64XX_UINTM_RXD_MSK (1 << S3C64XX_UINTM_RXD)
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| 211 | +#define S3C64XX_UINTM_ERR_MSK (1 << S3C64XX_UINTM_ERROR) |
184 | 212 | #define S3C64XX_UINTM_TXD_MSK (1 << S3C64XX_UINTM_TXD)
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185 | 213 |
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186 | 214 | /* Following are specific to S5PV210 */
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