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[FXML-4643] Lower arith.divui, arith.remui to EmitC (#211)
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mlir/lib/Conversion/ArithToEmitC/ArithToEmitC.cpp

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@@ -424,6 +424,38 @@ class ArithOpConversion final : public OpConversionPattern<ArithOp> {
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}
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};
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template <class ArithOp, class EmitCOp>
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class BinaryUIOpConversion final : public OpConversionPattern<ArithOp> {
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public:
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using OpConversionPattern<ArithOp>::OpConversionPattern;
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LogicalResult
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matchAndRewrite(ArithOp uiBinOp, typename ArithOp::Adaptor adaptor,
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ConversionPatternRewriter &rewriter) const override {
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Type newRetTy = this->getTypeConverter()->convertType(uiBinOp.getType());
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if (!newRetTy)
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return rewriter.notifyMatchFailure(uiBinOp,
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"converting result type failed");
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if (!isa<IntegerType>(newRetTy)) {
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return rewriter.notifyMatchFailure(uiBinOp, "expected integer type");
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}
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Type unsignedType =
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adaptIntegralTypeSignedness(newRetTy, /*needsUnsigned=*/true);
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if (!unsignedType)
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return rewriter.notifyMatchFailure(uiBinOp,
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"converting result type failed");
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Value lhsAdapted = adaptValueType(uiBinOp.getLhs(), rewriter, unsignedType);
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Value rhsAdapted = adaptValueType(uiBinOp.getRhs(), rewriter, unsignedType);
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auto newDivOp =
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rewriter.create<EmitCOp>(uiBinOp.getLoc(), unsignedType,
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ArrayRef<Value>{lhsAdapted, rhsAdapted});
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Value resultAdapted = adaptValueType(newDivOp, rewriter, newRetTy);
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rewriter.replaceOp(uiBinOp, resultAdapted);
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return success();
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}
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};
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template <typename ArithOp, typename EmitCOp>
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class IntegerOpConversion final : public OpConversionPattern<ArithOp> {
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public:
@@ -728,6 +760,8 @@ void mlir::populateArithToEmitCPatterns(RewritePatternSet &patterns,
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ArithOpConversion<arith::RemSIOp, emitc::RemOp>,
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ArithOpConversion<arith::MulFOp, emitc::MulOp>,
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ArithOpConversion<arith::SubFOp, emitc::SubOp>,
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BinaryUIOpConversion<arith::DivUIOp, emitc::DivOp>,
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BinaryUIOpConversion<arith::RemUIOp, emitc::RemOp>,
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IntegerOpConversion<arith::AddIOp, emitc::AddOp>,
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IntegerOpConversion<arith::MulIOp, emitc::MulOp>,
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IntegerOpConversion<arith::SubIOp, emitc::SubOp>,

mlir/test/Conversion/ArithToEmitC/arith-to-emitc-unsupported.mlir

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@@ -118,3 +118,19 @@ func.func @arith_shrui_i1(%arg0: i1, %arg1: i1) {
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%shrui = arith.shrui %arg0, %arg1 : i1
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return
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}
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// -----
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func.func @arith_divui_vector(%arg0: vector<5xi32>, %arg1: vector<5xi32>) -> vector<5xi32> {
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// expected-error @+1 {{failed to legalize operation 'arith.divui'}}
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%divui = arith.divui %arg0, %arg1 : vector<5xi32>
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return %divui: vector<5xi32>
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}
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// -----
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func.func @arith_remui_vector(%arg0: vector<5xi32>, %arg1: vector<5xi32>) -> vector<5xi32> {
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// expected-error @+1 {{failed to legalize operation 'arith.remui'}}
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%divui = arith.remui %arg0, %arg1 : vector<5xi32>
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return %divui: vector<5xi32>
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}

mlir/test/Conversion/ArithToEmitC/arith-to-emitc.mlir

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@@ -694,3 +694,21 @@ func.func @arith_index_castui(%arg0: i32) -> i32 {
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return %int : i32
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}
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// -----
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func.func @arith_divui_remui(%arg0: i32, %arg1: i32) -> i32 {
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// CHECK-LABEL: arith_divui_remui
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// CHECK-SAME: (%[[Arg0:[^ ]*]]: i32, %[[Arg1:[^ ]*]]: i32)
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// CHECK: %[[Conv0:.*]] = emitc.cast %[[Arg0]] : i32 to ui32
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// CHECK: %[[Conv1:.*]] = emitc.cast %[[Arg1]] : i32 to ui32
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// CHECK: %[[Div:.*]] = emitc.div %[[Conv0]], %[[Conv1]] : (ui32, ui32) -> ui32
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%div = arith.divui %arg0, %arg1 : i32
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// CHECK: %[[Conv2:.*]] = emitc.cast %[[Arg0]] : i32 to ui32
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// CHECK: %[[Conv3:.*]] = emitc.cast %[[Arg1]] : i32 to ui32
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// CHECK: %[[Rem:.*]] = emitc.rem %[[Conv2]], %[[Conv3]] : (ui32, ui32) -> ui32
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%rem = arith.remui %arg0, %arg1 : i32
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return %div : i32
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}

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