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1 parent f0bfa78 commit cb8bcc9Copy full SHA for cb8bcc9
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
@@ -288,13 +288,16 @@ void optc1_program_timing(
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if (optc1_is_two_pixels_per_containter(&patched_crtc_timing) || optc1->opp_count == 2)
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h_div = H_TIMING_DIV_BY2;
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+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
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if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
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if (optc1->opp_count == 4)
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h_div = H_TIMING_DIV_BY4;
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REG_UPDATE(OTG_H_TIMING_CNTL,
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OTG_H_TIMING_DIV_MODE, h_div);
- } else {
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+ } else
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+#endif
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+ {
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OTG_H_TIMING_DIV_BY2, h_div);
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}
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